The need for GPSDO’s type subsystems could possibly go away if every GPS receiver was able to afford a high-grade master oscillator. But until a small, low-cost atomic clock is developed, such systems will continue to be needed. If we look at the block diagram of our GPSDO (Fig.8.10) and compare to it to Fig.8.1, we see that the TIC function is replicatedoutsidethe receiver for use by the GPSDO PLL system.
This replication of this measurement system is due to the fact that the DO is not providing the receiver’s master clock signal. If we can make the DO signal drive the receiver’s Master Clock, then we do not need to build our own TIC as was done in for the GPSDO discussed above.Instead we can use the receiver reported rate and phase errors, which now are referenced directly to the DO. The precision and resolution of these reported errors is (should be) very high. It is quite difficult to match them with externally constructed circuits.
Figure8.11shows such a system that uses a DDS-based DO to provide not only the output 5/10 MHz output signal but also the receiver’s Master Clock signal. This architecture allows the GPSDO to use the measurements of Receiver Clock rate and Phase error directly with no external TIC circuitry needed. In the case shown here, two 48-bit DDSs are used, one to generate the master clock at 16.8 MHz and one to generate the 5-MHz output. In receivers where the master clock is 10 MHz, See Zarlink Chap. 9, the DDS for that clock can be omitted with the loss of rate and phase nulling for the receiver clock. If rate and phase nulling of the master clock for use by the receiver is not of interest, then the DDS for that function could also be replaced by a PLL operating on a VCXO.
The design presented here is primarily a rate only corrected output at 5 or10 MHz. The reason is that the high Q crystal filter on the 5 MHz output will introduce significant phase errors that can vary with temperature. The crystal filter is needed to remove close in spurious present on the DDS output.
If a divider were inserted on the produced 5 MHz so as to produce a 1-PPS signal, it would be found to have a phase offset and a wandering phase (with temperature) with respect to the 1 PPS from the receiver. This is an example of syntony as opposed to synchrony. If a low Q filter for the 5 MHz can be tolerated, the phase wanderings with temperature will become significantly smaller, perhaps small enough to where the 5 MHz becomes synchronous to the 1 PPS from the receiver, at least within the accuracy of receiver 1 PPS variation.
The master clock is now any 10 MHz clock signal that has enough stability and accuracy for the receiver to properly operate. To obtain a low rate error 5-MHz output, we simply program the DDS with a rate that accounts for the receiver reported rate error. This is possible since the GPS receiver is providing a rate error measurement of its master clock @16.8 MHz, which is a known rate and phase offset from the supplied 10 MHz clock. In short, we can think of the receiver reported rate and phase errors as being referenced to the 10 MHz Clock.
8.7 A Rate Corrected DDS 5/10 MHz Reference Based on Any 10 MHz Clock 157
Fig. 8.11 5/10Mhz GPSDO using 48 bit DDS’s
158 8 GPS Time and Frequency Reception
In order to produce a clean 5 MHz output from a DDS, we need to provide a clock frequency that is higher than 5 MHz by at least a factor of 3 and that is not an integer multiple of 5 MHz. DDS outputs near integer multiples of the DDS clock (i.e., Commensurate) have spurious frequency components that are very close to the desired output frequency. Multiplying the 10 MHz clock by 4 followed by a multiply/divide by 2/3 results in a DDS clock frequency of 26.6666 MHz. This DDS clock frequency is roughly five times that of desired output rate and is non-commensurate with 5 MHz.
To produce the 10-MHz output, the 5-MHz signal is doubled using a diode-based doubler with typically greater than 40 dB of fundamental rejection. A low Q, double-tuned bandpass at 10 MHz does the final spectrum clean up to produce the rate corrected 10 MHz output.
This design can also be used to drive the receivers 16.8 MHz rate error toward zero if desired, i.e., reported rate errors near zero. Doing so means that rate errors for the 5 MHz will need to reflect this change in reported rate error by backing out the rate error at 10-MHz input. The all-digital, high precision of the design makes this reverse type calculation possible. Driving the rate error to near zero on for the 16.8-MHz signal must be done very carefully for fear of upsetting the measurement of those same rate errors! Leaving the 16.8-MHz rate errors uncorrected has advantages when viewed from a measurement perspective, which isdo not disturb what you are measuring.
The rate control register of the DDS must have enough bits to provide the rate resolution needed. As DDS clock rate rises, the number of bits needed will increase.
For a DDS clock frequency of 80 MHz, at least 36 bits should be available in the DDS. A DDS with 48 bits is significantly more than needed.
The design presented here has multiple advantages over the GPSDO presented earlier;
• All Digital Rate and Phase Control Points.
• Can use a wide variety of 10 MHz Oscillator Clocks as a master reference.
• Uses Receiver-provided measurements of Rate and Phase Error.
• No external TIC circuitry needed.
• Can be used to drive receiver-reported rate error toward zero. In such a case 1 PPS Signal from receiver may have increased fidelity.
• The control loop can easily adapt to the stability of the 10-MHz reference used For the case where the receiver’s clock rate remains uncorrected, i.e., its dedicated DDS output rate control is static and will contain the rate errore, but we wish to correct the 5-MHz output rate, we can use the receiver reported rate error edirectly in the 5-MHz DDS calculations. For this case,eis reporting the estimate of rate error on the master oscillator.
The output rate of a DDS (or NCO) is:
fout¼½Mfclk=2N
8.7 A Rate Corrected DDS 5/10 MHz Reference Based on Any 10 MHz Clock 159
wherefclkis the clock rate input to the DDS, N the DDS Phase Register width andM the integer value of the DDS rate input to achievefoutrate.
The reported rate error,e, of the GPS receiver is also the scaled rate error on the DDS input clock. We can use the reported error to write thecorrectedDDS clock rate as:
fclk¼fclk nomþefclk nomwherefclk nomis thenominalrateof the DDS clock (wrt GPS)
¼fclk nomð1þeÞ
(8.10) We can find the nominal value ofM,Mnomthat will produce exactly the desired output rate when the rate error,e, is zero as:
Mnom¼ 2Nfout
=fclk nom (8.11)
whereMnomis the integer to obtainfoutwhene¼0
For the general case whereeis not zero, that is the imperfectfclkis the input to the DDS, we can findMfrom;
2Nfout
=fclk nom¼Mð1þeÞ (8.12)
Now using definition ofMnomfrom (8.10), we expressMin terms ofeandMnom; M¼Mnom=ð1þeÞwhich is as expected; as M¼Mnomwhen e¼0 (8.13) For the hardware implementation and errors as presented in Fig.8.11, we have;
fout¼5 MHz,N¼48,fclk_nom ¼26.6666666666 MHz,e¼+101.013 ns/s Mnom¼2485 MHz/26.6666666666 MHz (rounded to nearest integer)
¼52776558133380
M ¼52776558133380/(1 + 101.013109) M ¼52776552802262
withMat this value, the 5 MHz output is now corrected within the limits of the rate error eestimate. The round off errors using 48 bits are much smaller than precision ofe.
8.7.1 A Mechanical Model of Rate Corrected DDS 5/10 MHz Reference Based on Any 10 MHz Clock
Figure 8.12 shows a gear model of the rate corrected 5-MHz clock where the receiver’s clock remains uncorrected as in the above example. The multipliers of Fig.8.11are replaced by gear ratios of the same values which creates new clock dials. All the gear-driven dials are in a simple fixed-phase (integer) relationship
160 8 GPS Time and Frequency Reception
with the exception of the 16.8-MHz clock dial. This dial is produced by DDS and the ratio is an irrational number. The 16.8-MHz dial phase is highly incommensu-rate with the driving 80-MHz clock, but it’s phase is not random with respect to it.
All rates shown are nominal with the 10-MHz local clock as the reference.
The corrected 5-MHz clock dial is modeled as a rubber wheel with approximate ratio of 1/5.333333333[1+e]. The rubber wheel can slip so the phase of the 5-MHz dial is random with respect to the driving 26.66666666-MHz clock dial. If we continually adjust the ratio of the rubber wheel using the rate error information supplied by the GPS receiver, the average rate of the 5-MHz clock dial will follow GPS clock rate.
40MHz CLK
80MHz CLK
26.666MHz CLK
10MHz CLK LOCAL
16.8MHz CLK DDS
2:1 Ratio
4:1 Ratio 2/3
Ratio
1/4.7619...
Ratio
Adj.
Ratio Rubber Wheel
~1/5.333...
Rate Corrected 5MHz CLK
DDS
Fig. 8.12 Mechanical Gear Model of Rate Corrected 5 MHz Reference
8.7 A Rate Corrected DDS 5/10 MHz Reference Based on Any 10 MHz Clock 161