Low Pin Count (LPC)
Low Pin Count (LPC)
24.5 Integrated Pull-Ups and Pull-Downs
24.6 I/O Signal Planes and States
24.7 Functional Description
The PCH LPC interface supports the Low Pin Count Interface Specification. The bus operates at 24 MHz clock frequency.
24.7.1 LPC Cycle Types
GPP_A4 / LAD3
/ ESPI_IO3 I/O LPC Multiplexed Command, Address, Data. For LAD3, internal Pull-up is provided.
GPP_A5 / LFRAME# /
ESPI_CS# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
GPP_A9 / CLKOUT_LPC0 /
ESPI_CLK
O
Low Pin Count (LPC) Clock Outputs: Single-Ended 24-MHz output to various single load connectors/ devices.
GPP_A10 /
CLKOUT_LPC1 O Low Pin Count (LPC) Clock Outputs: Single-Ended 24-MHz output to various single load connectors/ devices.
GPP_A8 /
CLKRUN# I/O LPC Clock Run for control of CLKOUT_LPC[1:0]: Connects to peripherals that need to request clock restart or prevention of clock stopping.
GPP_A6 / SERIRQ /
ESPI_CS1# I/O This signal implements the serial interrupt protocol.
Note: An external Pull-up to V3.3S power rail is required.
GPP_A14 / SUS_STAT# / ESPI_RESET# O
LPC Mode - Suspend Status: This signal is asserted by the PCH to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes.
Signal Resistor Type Value Notes
LAD[3:0] Pull-up 15 - 40 kohm
Signal Name Power Plane During Reset* Immediately
after Reset* S3/S4/S5 Deep Sx LAD[3:0] Primary Internal Pull-up Internal Pull-up Undriven Off
LFRAME# Primary Driven High Driven High Driven Low Off
CLKOUT_LPC0 Primary Toggling Toggling Driven Low Off
CLKOUT_LPC1 Primary Toggling Toggling Driven Low Off
CLKRUN# Primary Undriven Undriven Undriven Off
SERIRQ Primary Undriven Undriven Undriven Off
SUS_STAT# Primary Driven Low Driven Low Driven Low Off
Note: *Reset reference for primary well pins is RSMRST#
Name Type Description
Low Pin Count (LPC)
24.7.2 Start Field Definition
24.7.3 Cycle Type/Direction (CYCTYPE + DIR)
The PCH always drives bit0 of this field to 0. Table 24-3 shows the valid bit encodings.
Table 24-1. LPC Cycle Types Supported
Cycle Type Comment
Memory Read 1 byte only—(Refer Note 1 below) Memory Write 1 byte only—(Refer Note 1 below)
I/O Read 1 byte only—The PCH breaks up 16-bit and 32-bit processor cycles into multiple 8-bit transfers.
I/O Write 1 byte only—The PCH breaks up 16-bit and 32-bit processor cycles into multiple 8-bit transfers.
Firmware Memory
Read 1 byte only
Firmware Memory
Write 1 byte only
Notes:
1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64 KB in size. and can be defined as being anywhere in the 4 GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in order to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the PCH returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
Table 24-2. Start Field Bit Definitions
Bits[3:0]
Encoding Definition
0000 Start of cycle for a generic target 1111 Stop/Abort: End of a cycle for a target.
Note: All other encodings are RESERVED.
Table 24-3. Cycle Type Bit Definitions
Bits[3:2] Bit1 Definition
00 0 I/O Read
00 1 I/O Write
01 0 Memory Read
01 1 Memory Read
11 x Reserved. If a peripheral performing a bus master cycle generates this value, the PCH aborts the cycle.
Note: All other encodings are RESERVED.
Low Pin Count (LPC)
24.7.4 Size
Bits[3:2] are reserved. The PCH always drives them to 00. Bits[1:0] are encoded as listed in Table 24-4.
24.7.4.1 SYNC
Valid values for the SYNC field are shown in Table 24-5.
24.7.5 SYNC Timeout
There are several error cases that can occur on the LPC interface. The PCH responds as defined in Section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the PCH.
24.7.6 SYNC Error Indication
The PCH responds as defined in Section 4.2.1.10 of the Low Pin Count Interface Specification Revision 1.1.
Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR# by reporting this into the Device 31 Error Reporting Logic.
Table 24-4. Transfer Size Bit Definition
Bits[1:0] Size
00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes)
10 Reserved
11 32-bit transfer (4 bytes)
Table 24-5. SYNC Bit Definition
Bits[3:0] Indication
0000 Ready: SYNC achieved with no error.
0101 Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not use this encoding. Instead, the PCH uses the long wait encoding.
0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the PCH for bus master cycles, rather than the Short Wait (0101).
1010 Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer.
Notes:
1. All other combinations are RESERVED.
2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC.
Low Pin Count (LPC)
24.7.7 LFRAME# Usage
The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1.
The PCH performs an abort for the following cases (possible failure cases):
• The PCH starts a Memory or I/O cycle, but no device drives a valid SYNC after four consecutive clocks.
• The PCH starts a Memory or I/O and the peripheral drives an invalid SYNC pattern.
• A peripheral drives an invalid value.
24.7.8 I/O Cycles
For I/O cycles targeting registers specified in the PCH’s decode ranges, the PCH performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where Pull-up resistors would keep the bus high if no device responds.
24.7.9 LPC Power Management
24.7.9.1 LPCPD# Protocol
Same timings as SUS_STAT#. Upon driving SUS_STAT# low, the PCH drives LFRAME#
low and tri-states (or drives low) LAD[3:0].
Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 μs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. The PCH asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time during a global reset. This is not inconsistent with the LPCPD# protocol.
24.7.10 Configuration and PCH Implications
24.7.10.1 LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH includes several decoders. During configuration, the PCH must be programmed with the same decode ranges as the peripheral. The decoders are programmed using the D 31:F0 configuration space.
Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.
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PCH and System Clocks