18 General Purpose Input and Output (GPIO)
18.4 Functional Description
18.4.1 GPIO Voltage
The following GPIO groups have the per-group voltage configurability. The voltage of all signals in the group is selected by both connecting the corresponding power supply pin and setting the associated soft strap to the desired voltage (3.3V or 1.8V), except for GPP_G group, whose voltage is selected via soft strap only.
— GPP_A, GPP_B, GPP_C, GPP_D, GPP_E, GPP_F, GPP_G, GPP_H, and GPP_K.
GPP_K22 VCCPGPPHK IMGCLKOUT0 out GP-In no yes(1) Z Z
GPP_K23 VCCPGPPHK IMGCLKOUT1 out GP-In no yes(1) Z Z
Deep Sleep Well Group (3.3 V Only) GPD0 VCCDSW_3
P3 BATLOW# in Native F1 no yes(1) Z Z
GPD1 VCCDSW_3
P3 ACPRESENT in Native F1 no yes(1) Refer note Z
Pin state during reset: In Deep Sx enabled configurations, pin is PD when PD is enabled (Refer ACPRES_PD_DSX_DIS bit); else Z GPD2 VCCDSW_3
P3 LAN_WAKE# in Native F1 no yes(1) Z Z
GPD3 VCCDSW_3
P3 PWRBTN# in Native F1 yes yes(1) PU PU
GPD4 VCCDSW_3
P3 SLP_S3# out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: H / GPIO: L
Native if SLP_S3# / GPD4 Signal Configuration soft strap = 0, else GPI
GPD5 VCCDSW_3
P3 SLP_S4# out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: H / GPIO: L
Native if SLP_S4# / GPD5 Signal Configuration soft strap = 0, else GPI
GPD6 VCCDSW_3
P3 SLP_A# out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: H / GPIO: L
Native if SLP_A# / GPD6 Signal Configuration soft strap = 0, else GPI
GPD7 VCCDSW_3
P3 GP-Out Reserved no no Z L
Strap read at rising edge of DSW_PWROK. External pull-up is required. Recommend 100 kohm.
This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction during strap sampling.
GPD8 VCCDSW_3
P3 SUSCLK out Native F1 no yes(2) L T
GPD9 VCCDSW_3
P3 SLP_WLAN# out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: L / GPIO: L
Native if SLP_WLAN# / GPD9 Signal Configuration soft strap = 0, else GPI
GPD10 VCCDSW_3
P3 SLP_S5# out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: H / GPIO: L
Native if SLP_S5# / GDP10 Signal Configuration soft strap = 0, else GPI
GPD11 VCCDSW_3
P3 LANPHYPC out Native F1/
GP-In no yes(2) Native F1: L /
GPIO: L Native F1: L / GPIO: L
Native if LAN PHY Power Control GPD11 Signal Configuration soft strap = 0, else GPI
Deglitch Legend
yes(1) - o/p Hi-Z, no internal weak pull during respective pin power sequencing
yes(2) - o/p Hi-Z, with integrated 20 kohm ± 30% pull-down during respective pin power sequencing
Pin State Legend
H- Driven High PU - Integrated 20 kohm ± 30% pull-up pulls pin high L - Driven Low PD - Integrated 20 kohm ± 30% pull-down pulls pin low Z - Hi-Z T - Toggling
Table 18-2. General Purpose I/O Signals (Sheet 9 of 9)
GPIO Power Rail Native Function
1
Native Dir
1
Native Function
2
Native Dir
2
Native Function
3
Native Dir
3
Native Function
4
Native Dir
4 Default Strap? Input Deglitch
Output Power Sequence
Deglitch
Pin State During Reset
Pin State Immediately
After Reset Notes
General Purpose Input and Output (GPIO)
18.4.2 Programmable Hardware Debouncer
Hardware debounce capability is supported on GPD3/PWRBTN# pad. The capability can be used to filter signal from switches and buttons if needed.
The period can be programmed from 8 to 32768 times of the RTC clock by
programming the Pad Configuration DW2 register. At 32 kHz RTC clock, the debounce period is 244 us to 1s.
18.4.3 Integrated Pull-ups and Pull-downs
All GPIOs have programmable internal pull-up/pull-down resistors (20 Kohm) which are disabled by default. The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming the corresponding PAD_CFG_DW1 register. Refer to Volume 2 (Register Info) for more details. The internal pull-up / pull down can only be implemented if the toggle rate of the GPIO is no more than 300 kHz.
Note that certain GPIOs used as pin straps have internal PU/PD enabled during reset by default. Refer Table 18-2 for info on which GPIO has integrated PU/PD enabled during reset.
18.4.4 GPPJ_RCOMP_1P8 Signal
The PCH implements the GPPJ_RCOMP_1P8 as an external bias resistor to ground. A 200 Ohm (+/- 1%) resistor to ground is required on the signal and this single resistor can be shared with SD_1P8_RCOMP and SD_3P3_RCOMP on the platform.
18.4.5 Interrupt / IRQ via GPIO Requirement
A GPIO, as an input, can be used to generate an interrupt/IRQ to the PCH. In this case, it is required that the pulse width on the GPIO must be at least 4 us for the PCH to recognize the interrupt.
18.4.6 SMI#/SCI and NMI
SCI capability is available on all GPIOs, while NMI and SMI capability is available only on select GPIOs.
Below are the PCH GPIOs that can be routed to generate SMI# or NMI:
• GPP_B14, GPP_B20, GPP_B23
• GPP_C[23:22]
• GPP_D[4:0]
• GPP_E[8:0]
• GPP_I[3:0]
• GPP_G[7:0] (support SMI# only).
18.4.7 Timed GPIO
The PCH supports 2 Timed GPIOs as native function (TIME_SYNC) that is multiplexed on GPIO pins. The intent usage of the Timed GPIO function is for time synchronization purpose.
General Purpose Input and Output (GPIO)
Timed GPIO can be an input or an output.
• As an input, a GPIO input event triggers the HW to capture the PCH Always Running Timer (ART) time in the Time Capture register. The GPIO input event must be asserted for at least 2 crystal oscillator clocks period in order for the event to be recognized.
• As an output, a match between the ART time and the software programmed time value triggers the HW to generate a GPIO output event and capture the ART time in the Time Capture register. If periodic mode is enabled, HW generates the periodic GPIO events based on the programmed interval. The GPIO output event is asserted by HW for at least 2 crystal oscillator clocks period.
Timed GPIO supports event counter. When Timed GPIO is configured as input, event counter increments by 1 for every input event triggered. When Timed GPIO is
configured as output, event counter increments by 1 for every output event generated.
The event counter provides the correlation to associate the Timed GPIO event (the nth event) with the captured ART time. The event counter value is captured when a read to the Time Capture Value register occurs.
When Timed GPIO is enabled, the crystal oscillator will not be shut down as crystal clock is needed for the Timed GPIO operation. As a result, SLP_S0# will not be asserted. This has implication to platform power (such as IDLE or S0ix power).
Software should only enable Timed GPIO when needed and disable it when Timed GPIO functionality is not required.
18.4.8 GPIO Blink (BK) and Serial Blink (SBK)
Certain GPIOs are capable of supporting blink and serial blink, indicated as BK and SBK respectively in the GPIO Signals table above. The BK and SBK are implemented as native functions multiplexed on the selected GPIOs. To enable BK or SBK on a GPIO having the capability, BIOS needs to select the assigned native function for BK or SBK on the GPIO.
18.4.9 GPIO Ownership
Any PCH GPIO can be owned either by the host or the Intel® ME. The designer can select GPIOs that are required by an Intel® ME feature using the Intel® ME FIT tool (available with Intel® ME FW releases). When selected and controlled by the Intel® ME, those GPIOs cannot be used by the host anymore.
§ §
Intel® Serial I/O Generic SPI (GSPI) Controllers