General Purpose I/O (D31:F0)

Functional Description

Once these registers are locked down, they become read-only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes from a ‘1’ to a ‘0’, a System Management Interrupt (SMI#) is generated, if enabled.

Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.

This ensures that only BIOS can change the GPIO configuration. If the GLE bit is cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is triggered and these registers will continue to be locked down.

5.13.5 Serial POST Codes Over GPIO

The PCH adds the extended capability allowing system software to serialize POST or other messages on GPIO. This capability negates the requirement for dedicated diagnostic LEDs on the platform.

5.13.5.1 Theory of Operation

For the PCH generation POST code serialization logic will be shared with GPIO. These GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component.

Figure 5-8 shows a likely configuration.

The anticipated usage model is that either the PCH or the SIO can drive a pin low to turn off an LED. In the case of the power LED, the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH can blink the LED by driving its corresponding pin low and subsequently tri-stating the buffer. The I/O buffer should not drive a ‘1’ when configured for this functionality and should be capable of sinking 24mA of current.

An external optical sensing device can detect the on/off state of the LED. By externally post-processing the information from the optical device, the serial bit stream can be recovered. The hardware will supply a ‘sync’ byte before the actual data transmission to allow external detection of the transmit frequency. The frequency of transmission should be limited to 1 transition every 1 μs to ensure the detector can reliably sample Figure 5-8. Serial POST Over GPIO Reference Circuit

Functional Description

the on/off state of the LED. To allow flexibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable using the DRS field in the GP_GB_CMDSTS register.

The serial bit stream is Manchester encoded. This choice of transmission ensures that a transition will be seen on every clock. The 1 or 0 data is based on the transmission happening during the high or low phase of the clock.

As the clock will be encoded within the data stream, hardware must ensure that the Z-0 and 0-Z transitions are glitch-free. Driving the pin directly from a flip-flop or through glitch-free logic are possible methods to meet the glitch-free requirement.

A simplified hardware/software register interface provides control and status information to track the activity of this block. Software enabling the serial blink capability should implement an algorithm referenced below to send the serialized message on the enabled GPIO.

1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared.

This will ensure that the GPIO is idled and a previously requested message is still not in progress.

2. Write the data to serialize into the GP_GB_DATA register.

3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit.

This may be accomplished using a single write.

Figure 5-8 shows the LEDs being powered from the suspend supply. By providing a generic capability that can be used both in the main and the suspend power planes, maximum flexibility can be achieved. A key point to make is that the PCH will not unintentionally drive the LED control pin low unless a serialization is in progress.

System board connections using this serialization capability are required to use the same power plane controlling the LED as the PCH GPIO pin. Otherwise, the PCH GPIO may float low during the message and prevent the LED from being controlled from the SIO. The hardware will only be serializing messages when the core power well is powered and the processor is operational.

Care should be taken to prevent the PCH from driving an active ‘1’ on a pin sharing the serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive a 1 would create a high-current path. A recommendation to avoid this condition involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be set first before changing the direction of the pin to an output. This sequence ensures the open-drain capability of the buffer is properly configured before enabling the pin as an output.

5.13.5.2 Serial Message Format

To serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is required to have its LED control pin in a high-Z state as well to allow the PCH to blink the LED (refer to Figure 5-8).

The three components of the serial message include the sync, data, and idle fields. The sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state (LED on) provides external hardware a known initial condition and a known pattern. In case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling logic to the encoded clock.

The data field is shifted out with the highest byte first (MSB). Within each byte, the most significant bit is shifted first (MSb).

The idle field is enforced by the hardware and is at least 2-bit times long. The hardware will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in hardware prevents time-based counting in BIOS as the hardware is immediately ready for the next serial code when the Go bit is cleared.

Note: The idle state is represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state will result in a final 0-1 transition on the output Manchester data. Two full bit times of idle correspond to a count of 4 time intervals; the width of the time interval is controlled by the DRS field.

The following waveform shows a 1-byte serial write with a data byte of 5Ah. The internal clock and bit position are for reference purposes only. The Manchester D is the resultant data generated and serialized onto the GPIO. Since the buffer is operating in open-drain mode, the transitions are from high-Z to 0 and back.

5.13.6 Peripheral IRQ

Eight suspend well GPIs and eight core well GPIs are mapped to the new peripheral IRQ pins that are routed to dedicated entries of IOxAPIC. To be used as peripheral IRQ, a GPIO pin needs to be configured to GPIO mode input direction (GPIO_USE_SEL=1 and GPIO_IO_SEL=1). For PIRQ mapping to APIC interrupt, refer to Table 5-12.

Figure 5-9. One-Byte Serial Write with Data Byte of 5Ah

Table 5-36. GPIO Mode Input to PIRQ Mapping (Sheet 1 of 2)

GPIO # PIRQ

Mapping GPIO Mode Power Well

8 PIRQI Suspend

9 PIRQJ Suspend

10 PIRQK Suspend

13 PIRQL Suspend

14 PIRQM Suspend

45 PIRQN Suspend

46 PIRQO Suspend

47 PIRQP Suspend

48 PIRQQ Core

49 PIRQR Core

50 PIRQS Core

Functional Description