General Purpose I/O Signals - 2 Signal Description

2 Signal Description

2.24 General Purpose I/O Signals

Table 2-24 summarizes the GPIOs in the PCH. The control for the GPIO signals is handled through an independent 128-byte I/O space. The base offset for this space is selected by the GPIO_BAR register in D31:F0 configuration space.

Note: Unused GPIs should be individually tied to power in order to ensure the input buffer is stable and not dissipating needless power. However, additional power savings (up to 5 μW per unused GPIO in some corner and high temperature cases) can be achieved if these unused GPIs are pulled down to ground instead of pulled up to power. In either case, the value of the resistor used should be in the range of 4.7 K to 50 K. The unused GPIs should remain configured in default GPI state and input sensing should be disabled by setting the corresponding GPI’s GPnConfigB.GPINDIS = 1.

Highlights of GPIO Features

1. All GPIO are powered from 3.3V rail but some are 1.8V input tolerant.

2. Only GPIO[31:0] are blink-capable.

3. When the default of a multiplexed GPIO is Native but the desired functionality is GPIO, care should be taken to ensure the signal is stable until it is initialized to GPIO functionality.

DDPC_AUXP I/O Port C: DisplayPort* Aux

DDPC_AUXN I/O Port C: DisplayPort* Aux Complement DDPC_HPD I Port C: HPD Hot-Plug Detect

DDPC_CTRLCLK I/O Port C: HDMI* Port C Control Clock DDPC_CTRLDATA I/O Port C: HDMI* Port C Control Data

Table 2-23. embedded DisplayPort* (eDP*) Backlight Control Signals

Name Type Description

eDP_VDDEN I/O

eDP Panel power Enable: Panel power control enable.

This signal is also called VDD_DBL in the CPIS specification and is used to control the VDC source of the panel logic.

eDP_BKLTEN I/O

eDP Backlight Enable: Panel backlight enable control for eDP This signal is also called ENA_BL in the CPIS specification and is used to gate power into the backlight circuitry.

eDP_BKLTCTL I/O

eDP Panel Backlight Brightness control: Panel brightness control for eDP.

This signal also called VARY_BL in the CPIS specification and is used as the PWM Clock input signal

eDP_HPD I eDP Port: Hot-Plug Detect

Note: The polarity of this signal is active high.

Note: eDP_VDDEN, eDP_BKLTEN, eDP_BKLTCTL can be left as no connect if eDP* is not used.

Table 2-22. Digital Display Signals (Sheet 2 of 2)

Name Type Description

4. In Table 2-24, Glitch-less Output means the signal is guaranteed to be stable (no glitch) during power on and when switching mode of operation. Glitch-less Input means the signal has built-in de-glitch protection.

5. All GPI are capable of generating IRQ interrupt based on software-configured level or edge-triggered event.

6. All GPI are capable of generating SCI.

7. Only GPI[47:32] are capable of NMI generation.

8. Only GPI[47:32] are capable of SMI# generation.

9. All Suspend Well (SUS) and Deep Sleep Well (DSW) GPI are capable of generating wake event.

10. GPIO Configuration registers within the Core Well are reset whenever PCH_PWROK is de-asserted.

11. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However, CF9h reset and SYS_RESET# events can be masked from resetting the Suspend well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers.

12. GPIO24 is an exception to the other GPIO signals in the Suspend Well and is not reset by CF9h reset (06h or 0Eh). Refer to offset 60h-63h: GP_RST_SEL[31:0]

13. All GPIO pins can be configured to have internal weak pull-up, weak pull-down or none, as described in Section 10.9.25, “GPnCONFIGB—GPIO Configuration B Register (Where n = GPIO Pin Number)” on page 474.

Table 2-24. General Purpose I/O Signals (Sheet 1 of 5)

Name Type Power

Well Default Internal Pull-Up/Pull-Down

Glitch-less

Description Input Output

GPIO0 I/O Core GPI No Yes Multiplexed with UART1_RXD

GPIO1 I/O Core GPI No Yes Multiplexed with UART1_TXD

GPIO2 I/O Core GPI No Yes Multiplexed with UART1_RTS#

GPIO3 I/O Core GPI No Yes Multiplexed with UART1_CTS#

GPIO4 I/O Core GPI Yes Yes Multiplexed with I2C0_SDA

(Note 2)

GPIO5 I/O Core GPI Yes Yes Multiplexed with I2C0_SCL

(Note 2)

GPIO6 I/O Core GPI Yes Yes Multiplexed with I2C1_SDA

(Note 2)

GPIO7 I/O Core GPI Yes Yes Multiplexed with I2C1_SCL

(Note 2)

GPIO8 I/O Sus GPI No Yes Unmultiplexed.

GPIO9 I/O Sus GPI No Yes Unmultiplexed

GPIO10 I/O Sus GPI No Yes Unmultiplexed

GPIO11 I/O Sus GPI Yes Yes Multiplexed with SMBALERT#

GPIO12 I/O DSW Native No Yes

Multiplexed with LAN_PHY_PWR_CTRL. GPIO/

Native functionality is controlled using soft strap. When configured as GPIO, default direction is Output (GPO).

(Note 4)

GPIO13 I/O Sus GPI No Yes Unmultiplexed

Signal Description

GPIO14 I/O Sus GPI No Yes Unmultiplexed

GPIO15 I/O Sus GPO

Pull-down (Disabled after

RSMRST# de-asserts)

No Yes

Unmultiplexed

This pin is a functional boot strap, see Section 2.27.

GPIO16 I/O Core GPI No Yes Unmultiplexed

GPIO17 I/O Core GPI No Yes Unmultiplexed

GPIO18 I/O Core GPI No Yes Multiplexed with PCIECLKRQ0#