6.9.1 ‘Anonymous Login’ Convention
11. Block Transfer (BT) Interface
11.6 Host to BMC Interface
The Host interface to the baseboard management controller (BMC) requires a block of 3 contiguous I/O locations on the system board. (A reference implementation fixes this at locations E4h:E6h. The interface circuitry will decode the lower 2 address lines, SA[1..0] ). A general-purpose chip select will be used to generate the select line for the interface, which is to reside in system I/O space. The I/O address offsets are defined as follows:
Table 11-1, BT Interface Registers
Offset Read Write
0 BT_CTRL - control register
1 BMC2HOST buffer HOST2BMC buffer
2 BT_INTMASK - interrupt mask register
The two buffers must meet the specified maximum message size requirements for all protocols supported on the messaging channels implemented on the BMC. Implementations can choose to provide more depth optionally. The GET_BT_INTERFACE_CAPABILITIES command is used to query for the actual implementation buffer depth.
The messaging protocol involves the host writing the command stream to the BT buffer, followed by setting a
“attention” bit in the BT control register. This automatically generates an interrupt to the baseboard management controller (BMC). The BMC then reads command packet from the BT buffer, and clears the attention bit. After processing the command, the BMC then writes the response data to the host-bound buffer. Finally, the BMC sets an outbound attention bit and generates an interrupt to the host (the host may optionally poll the attention bits, and may enable/disable the interrupts via a MASK register). Refer to Section 11.7 for a walk-through of the sequence of operations used for transfers on the BT interface.
There is no explicit requirement or recommendation for the hardware used to implement the interface. A discrete, custom, programmable array, or other implementation may be used at the discretion of the designer. As an example, some implementations have used a Xilinx* XC4003E Field Programmable Gate Array (FPGA) to implement the interface circuit because it provides on-chip user RAM that can be effectively used to implement the interface’s buffers. This implementation was able to provide 64-byte buffers.
11.6.1 BT Host Interface Registers
The Host BT interface provides an independent set of registers and interrupts to allow the Host driver to communicate with the baseboard management controller without conflicting with the O/S ACPI driver.
11.6.2 BT BMC to Host Buffer (BMC2HOST)
From the host side, this is a read-only buffer, which contains a command response stream from the embedded controller. The buffer must be a minimum of 64-bytes deep. This shares offset 1 of the I/O space with the
HOST2BMC buffer. Hence I/O read cycles from the host CPU remove data from this buffer, whereas write cycles from the BMC load data into this buffer.
11.6.3 BT Host to BMC Buffer (HOST2BMC)
From the host side, this is a write-only buffer to which the host writes a command stream to the baseboard
management controller. The buffer must be a minimum of 64-bytes deep. This shares offset 1 of the I/O space with the BMC2HOST buffer. Hence an I/O write cycles from the host CPU load data into this buffer, whereas read cycles from the BMC remove data from this buffer.
11.6.4 BT Control Register (BT_CTRL)
The host and the BMC use this register for various control functions defined below.
Figure 11-5, BT_CTRL Register format
7 6 5 4 3 2 1 0
B_BUSY H_BUSY OEM0 EVT_ATN B2H_ATN H2B_ATN CLR_RD_PTR CLR_WR_PTR
Table 11-2, BT_CTRL Register Bit Definitions
BIT R/W*
By Host
R/W*
By BMC
NAME FUNCTION
0 W W CLR_WR_PTR Clear Write Pointer. The host writes a 1 to clear the write pointer to the BT HOST2BMC buffer; this bit is always read back as 0.
Writing a 0 has no effect. Similarly, the BMC writes a 1 to clear the write pointer to the BT BMC2HOST buffer; this bit is always read back as 0. Writing a 0 has no effect. Clearing the pointer is defined as moving it to point to the start of the next valid buffer (typically the top of a single FIFO buffer).
1 W W CLR_RD_PTR Clear Read Pointer. The host writes a 1 to clear the read pointer to the BT BMC2HOST buffer; this bit is always read back as 0.
Writing a 0 has no effect. Similarly, the BMC writes a 1 to clear the read pointer to the BT HOST2BMC buffer; this bit is always read back as 0. Writing a 0 has no effect. Clearing the pointer is defined as moving it to point to the start of the next valid buffer (typically the top of a single FIFO buffer).
2 R/S Write 1 to
set bit;
0 no effect
R/C Write 1 to
clear bit;
0 no effect
H2B_ATN Reset State=0
Host to BMC Attention. When the host writes a 1 to this bit, an interrupt is generated to the baseboard management controller.
The host should set this bit when it has completed writing a message stream to the HOST2BMC buffer. The baseboard management controller clears this bit after it has set the B_BUSY bit. The host may poll the H2B_ATN bit to determine that the baseboard management controller has acknowledged the command. The capability to operate in a polled mode by the BMC is optional.
3 R/C Write 1 to
clear bit;
0 no effect
R/S Write 1 to
set bit;
0 no effect
B2H_ATN Reset State=0
BMC to Host Attention. The BMC sets this bit when it has
completed writing a message response stream to the BMC2HOST buffer. The host may poll the B2H_ATN bit to determine that the baseboard management controller has finished writing a message response stream to the BMC2HOST buffer. After setting H_BUSY, the host should clear this bit to acknowledge receipt of the message response. This bit can be enabled to generate an interrupt to the host by setting the B2HI_EN bit in the INTMASK register.
4 R/C Write 1 to
clear bit:
0 no effect
R/S Write 1 to
set bit;
0 no effect
SMS_ATN Reset State=0
SMS Attention. The BMC sets this bit when it has detected and queued an SMS message that must be reported to the host. This allows the host to distinguish between command responses and SMS messages from the baseboard management controller. This bit can be enabled to generate an interrupt to the host by a host set of the B2HI_EN bit in the INTMASK register. The host clears this bit by writing a 1 to it.
BIT R/W*
By Host
R/W*
By BMC
NAME FUNCTION
5 R/S Write 1 to
set bit;
0 no effect
R/C Write 1 to
clear bit:
0 no effect
OEM0 Reset State=0
Reserved for definition by platform. Generic IPMI software must write this bit as 0, and ignore the value on read. The OEM0 bit should be able to generate an interrupt to the BMC when written by the host but is not required (polled mode is acceptable).
Typical usage is a “heartbeat” mechanism from/to the host; the host sets OEM0 to interrupt the BMC and then polls this bit to be cleared (BMC is alive and responded to the interrupt). The BMC FW completes the acknowledge cycle by clearing OEM0 upon receipt of the interrupt (host is alive).
6 R/S/C Write 1 to
toggle
R H_BUSY Reset State=0
Host Busy. This bit is set/cleared by the Host to indicate that it is busy processing response/event data from the BMC or cannot accept response/event data at this time. It is set to 1 if the host writes a 1 when H_BUSY=0, cleared if the host writes a 1 when H_BUSY=1; there is no effect if the host writes a 0 to this bit (toggle implementation). The BMC will need to verify that this bit is cleared before sending a response or event message.
7 R R/S/C Write 1 to toggle
B_BUSY Reset State=1
Baseboard Management Controller Busy. This bit is set/cleared by the BMC to indicate that it is busy processing
command/request data from the Host or cannot accept
command/request data at this time. It is set to 1 if the BMC writes 1 when B_BUSY=0, cleared if the BMC writes 1 when B_BUSY=1;
there is no effect if the BMC writes 0 to this bit (toggle
implementation). . The initial state of this bit should be set to 1 so that the BMC side driver can initialize and prepare to accept Host traffic before the Host attempts to use it the first time.
* R=read; W=write; S=set; C=clear
11.6.5 BT Interrupt Mask Register (INTMASK)
This register is used by the host to control which interrupts can be generated by the baseboard management controller.
Figure 11-6, BT_INTMASK Register format
7 6 5 4 3 2 1 0
BMC_HWRST rsvd rsvd OEM3 OEM2 OEM1 B2H_IRQ B2H_IRQ_EN
Table 11-3, BT_INTMASK Register Bit Definitions
BIT R/W NAME FUNCTION
0 R/W B2H_IRQ_EN BMC to HOST Interrupt Enable. The interrupt is generated by the BMC-BT interface if B2H_IRQ_EN is set (1) and either the B2H_ATN or EVT_ATN bits are set by the BMC.
1 R/W B2H_IRQ BMC to HOST Interrupt Active. This bit reflects the state of the interrupt line to the host, and therefore can only become set (1) if by B2H_IRQ_EN is set and the interrupt condition has occurred.
On a read: 0 = interrupt to host not active; 1 = interrupt to host active
On a write: 0 = no effect; 1 = clear interrupt (this is the source of the INT, and is immediately cleared by the O/S driver). This only clears the interrupt for the system interface. Other interrupts may require clearing flags internal to the BMC.
If bit is 0, then a rising edge on B2H_ATN or EVT_ATN sets this to 1. If already 1, then no affect.
2 R/W OEM1 Reserved for definition by platform manufacturer for BIOS/SMI Handler use.
Generic IPMI software must write this bit as 0, and ignore the value on read.
3 R/W OEM2 Reserved for definition by platform manufacturer for BIOS/SMI Handler use.
Generic IPMI software must write this bit as 0, and ignore the value on read.
4 R/W OEM3 Reserved for definition by platform manufacturer for BIOS/SMI Handler use.
Generic IPMI software must write this bit as 0, and ignore the value on read.
5 R/W Reserved Reserved for future definition by IPMI. Write as 0, ignore value on read.
6 R/W Reserved Reserved for future definition by IPMI. Write as 0, ignore value on read.
7 R/W BMC_HWRST Host to Baseboard Management Controller Reset. (OPTIONAL)
Always read back as zero. Writing a 1 to this bit will cause a hardware reset of the BMC. This is non-sticky; writing zero has no effect. This bit, if provided, is intended for to be used for error recovery by the host if loss of communication with the BMC occurs.