Intel® Serial I/O Generic SPI (GSPI) Controllers
19 Intel ® Serial I/O Generic SPI
Intel® Serial I/O Generic SPI (GSPI) Controllers
19.4 Integrated Pull-Ups and Pull-Downs
19.5 I/O Signal Planes and States
19.6 Functional Description
19.6.1 Features
The GSPI interfaces support the following features:
• Full duplex synchronous serial interface
• Support Motorola’s SPI protocol
• Operates in master mode only
Signal Resistor Type Value Notes
GSPI0_MOSI Pull Down 20 kohm ±
30% Internal Pull Down is not enabled by default.
GSPI1_MOSI Pull Down 20 kohm ±
30% Internal Pull Down is not enabled by default.
GSPI2_MOSI Pull Down 20 kohm ±
30% Internal Pull Down is not enabled by default.
GSPI0_MISO Pull Down 20 kohm ±
30%
GSPI1_MISO Pull Down 20 kohm ±
30%
GSPI2_MISO Pull Down 20 kohm ±
30%
Signal Name Power Plane During Reset1 Immediately
after Reset1 S3/S4/S5 Deep Sx GSPI2_CS0#,
GSPI2_CS1#, GSPI1_CS0#, GSPI1_CS1#, GSPI0_CS0#, GSPI0_CS1#
Primary Undriven Undriven Undriven OFF
GSPI2_CLK, GSPI1_CLK, GSPI0_CLK
Primary Undriven Undriven Undriven OFF
GSPI2_MISO, GSPI1_MISO, GSPI0_MISO
Primary Undriven Undriven Undriven OFF
GSPI2_MOSI, GSPI1_MOSI, GSPI0_MOSI
Primary Internal Pull
down Driven Low Internal Pull
down OFF
Notes:
1. Reset reference for primary well pins is RSMRST#.
Intel® Serial I/O Generic SPI (GSPI) Controllers
19.6.2 Controller Overview
The generic SPI controllers can only be set to operate as a master.
The processor or DMA accesses data through the GSPI port’s transmit and receive FIFOs.
A processor access takes the form of programmed I/O, transferring one FIFO entry per access. Processor accesses must always be 32 bits wide. Processor writes to the FIFOs are 32 bits wide, but the PCH will ignore all bits beyond the programmed FIFO data size. Processor reads to the FIFOs are also 32 bits wide, but the receive data written into the Receive FIFO is stored with ‘0’ in the most significant bits (MSB) down to the programmed data size.
The FIFOs can also be accessed by DMA, which must be in multiples of 1, 2, or 4 bytes, depending upon the value, and must also transfer one FIFO entry per access.
For writes, the PCH takes the data from the transmit FIFO, serializes it, and sends it over the serial wire to the external peripheral. Receive data from the external peripheral on the serial wire is converted to parallel words and stored in the receive FIFO.
A programmable FIFO trigger threshold, when exceeded, generates an interrupt or DMA service request that, if enabled, signals the processor or DMA respectively to empty the Receive FIFO or to refill the Transmit FIFO.
The GSPI controller, as a master, provides the clock signal and controls the chip select line. Commands codes as well as data values are serially transferred on the data signals. The PCH asserts a chip select line to select the corresponding peripheral device with which it wants to communicate. The clock line is brought to the device whether it is selected or not. The clock serves as synchronization of the data communication.
19.6.3 DMA Controller
The GSPI controllers have an integrated DMA controller.
19.6.3.1 DMA Transfer and Setup Modes The DMA can operate in the following modes:
1. Memory to peripheral transfers. This mode requires that the peripheral control the flow of the data to itself.
2. Peripheral to memory transfer. This mode requires that the peripheral control the flow of the data from itself.
The DMA supports the following modes for programming:
1. Direct programming. Direct register writes to DMA registers to configure and initiate the transfer.
2. Descriptor based linked list. The descriptors will be stored in memory. The DMA will be informed with the location information of the descriptor. DMA initiates reads and programs its own register. The descriptors can form a linked list for multiple blocks to be programmed.
3. Scatter Gather mode.
Intel® Serial I/O Generic SPI (GSPI) Controllers
19.6.3.2 Channel Control
• The source transfer width and destination transfer width are programmable. The width can be programmed to 1, 2, or 4 bytes.
• Burst size is configurable per channel for source and destination. The number is a power of 2 and can vary between 1,2,4,...,128. This number times the transaction width gives the number of bytes that will be transferred per burst.
• Individual Channel enables. If the channel is not being used, then it should be clock gated.
• Programmable Block size and Packing/Unpacking. Block size of the transfer is programmable in bytes. The block size is not limited by the source or destination transfer widths.
• Address incrementing modes. The DMA has a configurable mechanism for computing the source and destination addresses for the next transfer within the current block. The DMA supports incrementing addresses and constant addresses.
• Flexibility to configure any hardware handshake sideband interface to any of the DMA channels.
• Early termination of a transfer on a particular channel.
19.6.4 Reset
Each host controller has an independent rest associated with it. Control of these resets is accessed through the Reset Register.
Each host controller and DMA will be in reset state once powered ON and require SW (BIOS or driver) to write into the corresponding reset register to bring the controller from reset state into operational mode.
19.6.5 Power Management
19.6.5.1 Device Power Down Support
In order to power down peripherals connected to the PCH GSPI bus, the idle configured state of the I/O signals must be retained to avoid transitions on the bus that can affect the connected powered peripheral. Connected devices are allowed to remain in the D0 active or D2 low power states when the bus is powered off (power gated). The PCH HW will prevent any transitions on the serial bus signals during a power gate event.
19.6.5.2 Latency Tolerance Reporting (LTR)
Latency Tolerance Reporting is used to allow the system to optimize internal power states based on dynamic data, comprehending the current platform activity and service latency requirements. However, the GSPI bus architecture does not provide the architectural means to define dynamic latency tolerance messaging. Therefore, the interface supports this by reporting its service latency requirements to the platform power management controller via LTR registers.
Intel® Serial I/O Generic SPI (GSPI) Controllers
requirements. In this scheme, the latency requirement is a function of the
controller state. The latency for transmitting data to/from its connected device at a given rate while the controller is active is representative of the active latency requirements. On the other hand if the device is not transmitting or receiving data and idle, there is no expectation for end to end latency.
2. Driver Control. This scheme is used for usage models in which the controller state does not inform the platform correctly of the current latency requirements. If the FIFOs of the connected device are much smaller than the controller FIFOs, or the connected device’s end-to-end traffic assumptions are much smaller than the latency to restore the platform from low power state, driver control should be used.
19.6.6 Interrupts
GSPI interface has an interrupt line which is used to notify the driver that service is required.
When an interrupt occurs, the device driver needs to read both the host controller and DMA interrupt status and transmit completion interrupt registers to identify the interrupt source. Clearing the interrupt is done with the corresponding interrupt register in the host controller or DMA.
All interrupts are active high and their behavior is level interrupt.
19.6.7 Error Handling
Errors that might occur on the external GSPI signals are comprehended by the host controller and reported to the interface host controller driver through the MMIO registers.
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