Interrupt Interface
Interrupt Interface
22.6 Functional Description
The PCH supports both APIC and PIC modes.
Interrupt sharing from the perspective of the Interrupt Controller that receives the Interrupts is limited to IRQ 0-23.
• Shareable interrupts requires the Interrupt Controller to track the Assert/De-assert Sideband message from each interrupt source. The Interrupt Controller achieves this through Source ID decode of the message.
• Maintains backwards compatibility with the prior generations where only the lower 24 IRQs are available to support Interrupt Sharing.
• Interrupts are dedicated and not shareable from the perspective of the Interrupt Controller for IRQ 24-119. In other words, not more than 1 Interrupt Initiator is allowed to be assigned to the same IRQ# for IRQ 24-119. For example, GPIO (multi-cause Interrupt Initiator) and Intel® Serial I/O interfaces (I2C, UART, GSPI) (multi-function Interrupt Initiator) should not both generate Assert/De-assert IRQn that maps to IRQ24.
• Possible multi-cause Interrupt Initiator that maps to IRQ24-119 are GPIO, eSPI, and so on.
• Possible multi-function Interrupt Initiators that maps to IRQ24-119 are HD Audio, I2C/UART/GSPI (Intel Serial I/O Interfaces), ISH, and so on.
Interrupt Sharing Compliance Requirement for the Interrupt Initiator are as follows:
1. For multi-cause Initiators (Multiple Interrupt Cause from Single Source and Single Sideband (SB) Port ID, e.g. GPIO, eSPI): If more than 1 interrupt cause has to use the same IRQ#, it has to be aggregated or guaranteed through BIOS/SW to assign a unique IRQ per Interrupt Cause.
2. For multi-function devices (1 Interrupt Cause per Source but many Sources are behind Single SB Port ID, example, Intel® Serial I/O interfaces (I2C, UART, GSPI)):
Again if sharing is needed, the interrupts have to be aggregated or guaranteed through SW to ensure a unique IRQ is assigned per Interrupt Cause.
3. IPs that have 1:1 mapping to the IRQ# such as eSPI and LPC are not impacted by this requirement. For eSPI, it is expected that the EC devices aggregate the interrupts before these are communicated to eSPI.
4. Single-cause or Single-function device behind a unique SB Port ID is not subjected to this requirement.
Only level-triggered interrupts can be shared. PCI interrupts (PIRQs) are inherently shared on the board; these should, therefore, be programmed as level-triggered.
The following tables show the mapping of the various interrupts in Non-APIC and APIC modes.
Table 22-1. Interrupt Options - 8259 Mode (Sheet 1 of 2)
IRQ# Pin SERIRQ PCI
Message Internal Modules
Interrupt Interface
3:7 PIRQA Yes Yes Option for configurable sources including PIRQx, GPIO, eSPI and internal PCI/ACPI devices
8 No No No RTC, HPET#1
9:10 PIRQA Yes Yes Option for configurable sources including PIRQx, GPIO, eSPI, internal PCI/ACPI devices, SCI and TCO.
11 PIRQA Yes Yes Option for configurable sources including PIRQx, GPIO, eSPI, internal ACPI devices, SCI, TCO, HPET
#2
12 PIRQA Yes Yes Option for configurable sources including PIRQx, GPIO, eSPI, internal ACPI devices, HPET#3 13 No No Yes Option for configurable sources including GPIO,
eSPI, internal ACPI devices
14:15 PIRQA Yes Yes Option for configurable sources including PIRQx, GPIO, eSPI and internal ACPI devices
Notes:
1. 8259 Interrupt Request Lines 0, 2 and 8 are non-shareable and dedicated. Only one interrupt source is allowed to use the Interrupt Request Line at any one time.
2. If an interrupt is used for PCI IRQ [A:H], SCI, or TCO, it should not be used for ISA-style interrupts (via SERIRQ).
3. In 8259 mode, PCI interrupts are mapped to IRQ3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15. It can be programmed via PIRQ[A-H] Routing Control at ITSS Private CR + Offset 3100h-3107h.
Table 22-2. Interrupt Options - APIC Mode (Sheet 1 of 2)
IRQ# Pin SERIRQ PCI
Message IRQ
Sharable? Internal Modules
0 No No No No Cascade from 8259 #1
1 No Yes No Yes Option for configurable sources
including GPIO, eSPI, internal ACPI/
PCI devices
2 No No No No 8254 Counter 0, HPET #0 (legacy
mode)
3:7 No Yes No Yes Option for configurable sources
including GPIO, eSPI, internal ACPI/
PCI devices
8 No No No No RTC, HPET #1 (legacy mode)
9:10 No Yes No Yes Option for configurable sources
including GPIO, eSPI, internal ACPI/
PCI devices, SCI and TCO
11 No Yes No Yes Option for configurable sources
including GPIO, eSPI, internal ACPI/
PCI devices, SCI, TCO, HPET #2
12 No Yes No Yes Option for configurable sources
including GPIO, eSPI, internal ACPI/
PCI devices, HPET#3
13 No No No Yes Option for configurable sources
including GPIO, eSPI and internal ACPI/PCI devices
14:15 No Yes No Yes Option for configurable sources
including GPIO, eSPI and internal ACPI/PCI devices
16 PIRQA PIRQA Yes Yes Option for configurable sources including internal PIRQA, GPIO, eSPI and internal ACPI/PCI devices
Table 22-1. Interrupt Options - 8259 Mode (Sheet 2 of 2)
IRQ# Pin SERIRQ PCI
Message Internal Modules
Interrupt Interface
The following signals are associated with the Interrupt Logic.
17:19 No PIRQ[B-D] Yes Yes Option for configurable sources including internal PIRQ[B-D], GPIO, eSPI and internal ACPI/PCI devices
20:23 No No No Yes
Option for configurable sources including internal PIRQ[E-H], GPIO, eSPI, SCI, TCO, internal ACPI/PCI devices and HPET
24:119 No No No No Option for configurable sources
including GPIO, eSPI and internal ACPI/PCI devices
Notes:
1. Interrupts 24 through 119 are dedicated and not shareable from the perspective of the Interrupt Controller. Not more than 1 Interrupt source is allowed to be assigned to the same IRQ#. For example, GPIO and Intel® Serial I/O interfaces (I2C, UART, GSPI) should not generate Assert/Deassert_IRQn that maps to IRQ24. Although dedicated, Interrupts 24 through 119 can be configured to be level or edge-triggered.
2. If an interrupt is used for PCI IRQ [A:H], SCI, or TCO, it should not be used for ISA-style interrupts (via SERIRQ).
3. In APIC mode, the PCI interrupts [A:H] are directly mapped to IRQ[16:23].
4. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15, and 24 through 119 receive high internal interrupt sources; interrupts 16 through 23 receive active-low internal interrupt sources.
5. The internal ACPI/PCI devices refer to PCI/PCIe devices configured to the ACPI or PCI function mode. If in ACPI function mode, the device interrupt is map directly to one of the available IRQ. If in PCI function mode, the device interrupt is map to INT[A-D] and then to the IRQ before these devices issue the Interrupt Message using Assert/Deassert_IRQn.
6. PCI Message refers to the downstream Assert/Deassert_INT[A-D] messages forwarded from the processor complex.
Table 22-2. Interrupt Options - APIC Mode (Sheet 2 of 2)
IRQ# Pin SERIRQ PCI
Message IRQ
Sharable? Internal Modules
Table 22-3. Interrupt Logic Signals
Signal Name C3 S3 S5
SERIRQ Can be running Off Off
PIRQA# Can go active Off Off
Interrupt Interface