5 Functional Description
5.4 Low Pin Count (LPC) Bridge (with System and Management Functions) (D31:F0)Management Functions) (D31:F0)
The LPC bridge function of the PCH resides in PCI D31:F0. In addition to the LPC bridge function, D31:F0 contains other functional units including Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, and so forth.) are described in their respective sections.
Note: The LPC bridge cannot be configured as a subtractive decode agent.
5.4.1 Low Pin Count (LPC) Interface
The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-4.
Note: The PCH implements all of the signals that are shown as optional, but peripherals are not required to do so.
5.4.1.1 LPC Cycle Types
The PCH implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. Table 5-3 shows the cycle types supported by the PCH.
Figure 5-4. Low Pin Count (LPC) Interface Diagram
Table 5-3. Low Pin Count (LPC) Cycle Types Supported (Sheet 1 of 2)
Cycle Type Comment
Memory Read 1 byte only—(See Note 1 below) Memory Write 1 byte only—(See Note 1 below)
I/O Read 1 byte only—The PCH breaks up 16-bit and 32-bit processor cycles into multiple 8-bit transfers.
I/O Write 1 byte only—The PCH breaks up 16-bit and 32-bit processor cycles into multiple 8-bit transfers.
5.4.1.2 Start Field Definition
5.4.1.3 Cycle Type/Direction (CYCTYPE + DIR)
The PCH always drives Bit 0 of this field to 0. Table 5-5 shows the valid bit encodings.
5.4.1.4 Size
Bits 3:2 are reserved. The PCH always drives them to 00. Bits 1:0 are encoded as listed in Table 5-6.
Bus Master Read Can be 1, 2 or 4 bytes—(See Note 2 below) Bus Master Write Can be 1, 2 or 4 bytes—(See Note 2 below) Notes:
1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64KB in size and can be defined as being anywhere in the 4GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the operating system in order to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the PCH returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address where A1 and A0 are both 0).
Table 5-4. Start Field Bit Definitions
Bits[3:0]
Encoding Definition
0000 Start of cycle for a generic target.
1111 Stop/Abort: End of a cycle for a target.
Note: All other encodings are RESERVED.
Table 5-3. Low Pin Count (LPC) Cycle Types Supported (Sheet 2 of 2)
Cycle Type Comment
Table 5-5. Cycle Type Bit Definitions
Bits[3:2] Bit[1] Definition
00 0 I/O Read
00 1 I/O Write
01 0 Memory Read
01 1 Memory Read
11 x Reserved. If a peripheral performing a bus master cycle generates this value, the PCH aborts the cycle.
Note: All other encodings are RESERVED.
Table 5-6. Transfer Size Bit Definition
Bits[1:0] Size
00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes)
10 Reserved—The PCH never drives this combination.
11 32-bit transfer (4 bytes) Note: All other combinations are RESERVED.
Functional Description
5.4.1.5 SYNC
Valid values for the SYNC field are shown in Table 5-7.
5.4.1.6 SYNC Timeout
There are several error cases that can occur on the LPC interface. The PCH responds as defined in Section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the PCH.
5.4.1.7 SYNC Error Indication
The PCH responds as defined in Section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1.
Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by reporting this into the Device 31 Error Reporting Logic.
5.4.1.8 LFRAME# Usage
The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1.
The PCH performs an abort for the following cases (possible failure cases):
• The PCH starts a Memory or I/O cycle, but no device drives a valid SYNC after four consecutive clocks.
• The PCH starts a Memory or I/O and the peripheral drives an invalid SYNC pattern.
• A peripheral drives an invalid value.
5.4.1.9 I/O Cycles
For I/O cycles targeting registers specified in the PCH decode ranges, the PCH performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.
Table 5-7. SYNC Bit Definition
Bits[3:0] Indication
0000 Ready: SYNC achieved with no error.
0101 Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not use this encoding. Instead, the PCH uses the Long Wait encoding (see next encoding below).
0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the PCH for bus master cycles, rather than the Short Wait (0101).
1010 Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer.
Notes:
1. All other combinations are RESERVED.
2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC.
5.4.1.10 LPC Power Management LPCPD# Protocol
Same timings as SUS_STAT#. Upon driving SUS_STAT# low, the PCH drives LFRAME#
low, and tri-states (or drives low) LAD[3:0].
Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 μs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power states that do not include asynchronous reset events. The PCH asserts both
SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
5.4.1.11 Configuration and PCH Implications LPC I/F Decoders
To allow the I/O cycles and memory-mapped cycles to go to the LPC interface, the PCH includes several decoders. During configuration, the PCH must be programmed with the same decode ranges as the peripheral. The decoders are programmed using the D 31:F0 configuration space.
Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.