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V N l J J o u r n a l o f S c i e n c c , M a t h e m a t i c s - P h y s i c s 27 ( 2 0 1 1 ) 1 2 3 - 13 0

Detection o f the location o f the hazard during and after the design o f combinational circuits

Nguyen Quy Thuong

VNU, Ỉ4 4 Xuan Thuy, Can Giav, Hanoi, Vietnam Received 14 April 2011

A b stract. Delay fault and glitch fault cause hazards that are structure hazard and function hazard.

During design process we can use many methods to identify and remove structural hazard [1-2], [3]. However, with function hazards, determination and remove much more difficult. In this paper we introduce a new solution to determine the structure hazard by the Truth table - Matrix mathematics M ethod and method for determining function hazard over how to determine crosstalk fault [4-71.

Keywords: Structure hazard, function hazard, truth table, multiplication matrix, hazard - algebra, crosstalk fault, glitch.

1. Introduction

D e te ctin g , lo c a tin g a n d rem o v in g h a zard s in a digital circu its is the c o m p ellin g w o rk o f a designer.

K a rn a u g h m ap [8 ] w a s u se d very often to d esig n d igital circu its th at are c o m b in atio n al a n d sequence;

sy n c h ro n o u s an d a s y n c h ro n o u s w ith h azard - free.

John K n ig h t [1], [3], T h u o n g N .Q [2] ap p lied h a z a rd - alg eb ra m eth o d for the d e sig n o f digital c ircu its. I f a c irc u it h a s a hazard , then function o f the c irc u it w ill be reduced to o n e o f th e se form s

X X , X 4- X , x x + x a n d (x + x)x . H azard - alg eb ra m eth o d can d ete c t and m ask h a z a rd in both

c o m b in a tio n a l a n d s e q u e n c e circuits.

T o in v e stig a te h a z a rd in co m b in a tio n a l circu its w ith E X - O R gates, E .c . T an and M .H . H o [9]

b u ilt m atrix m e th o d th a t g en erate a set o f v ariab les o f all nodes in each gate level o f a circuit p ro g re s s iv e ly u ntil it re a c h e s th e o u tp u t o f circuit. H o w e v er, th is m ethod has notyet sh o w exact lo ca tio n o f h a z a rd s a n d w h en d y n a m ic h azard is d e p e n d en t on static logic 0 “ h azard o r d e p e n d e n t on static logic 1 - hazard. [4 -7 ], [ 10, 11] sh o w s the test m ethods for crosstalk fault in d u ced glitch

fault. Through crosstalk fault, we have function Hazards can be determined, that appears only after the circuit was put into use.

In th is p a p e r a n e w so lu tio n is p ro p o se d to in v estig ate stru ctu re h azard s in c o m b in a tio n a l circuits th at is b a s e d o n c o m b in a tio n o f truth tab le, m atrix m ath em atics and h azard - alg eb ra to d e te c t stru ctu re

E-mail: cp4m ua@ yahoo.com .vn

123

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124 N.Q. T h u o n g / VNU Journal o f Science, Mathematics - Physics 27 (20Ỉ Ỉ) Ỉ2 3 -Ỉ3 0

h a z ard s. T his p a p e r also p o in ts out the m ethod o f d e te rm in in g th e fu n ctio n h a zard s via the d e te rm in a tio n o f cro sstalk fault. T h e stru ctu re o f this p a p e r is as fo llo w s. S ectio n 2 g iv es b a c k g ro u n d on h a z a rd algebra, the d iffe re n c e b etw een B o olean alg eb ra and H a z a rd alg eb ra; rela tio n s b etw een m a t ì x m ath e m a tic s a n d tru th table an d circu it eq uation o f function; the test m e th o d s to d ete rm in e the c ro s s ta lk fault, w hich is to d e te rm in e fu nction h azard in the d igital circu it. S ection 3 gives the form al p ro b le m sta te m e n t to be so lv ed , an d an intuitive o v erv iew o f the n ew m eth o d as the ru le s to d elect s ừ u c tu re h azard s o f so p h istic a te d form s (in c lu d in g SO P and P O S ). S e c tio n 4 gives th e m ode o f d e te rm in in g the fu nction h a z a rd in th e c irc u it w as put into use.

2. B ackground

T h e p o ten tial for a g lilch in a com b in atio n al circu it is ca lled a hazard . H azard s fall into tw o c la sse s: fu nction h azard s an d stru ctu ral hazard s. S tructure h azard co u ld be d e te c te d and rem o v ed even d u rin g the design p ro ce ss b u t function hazard that can d elect o n ly th e c irc u it a fte r hav in g taken into use an d the rem oval o f fu n ctio n h azaru is m ore difficu lt th an o f stru c tu ra l h a z ard . T h is sectio n focuses o n th e p ro b le m to o f h azard s, h a z a rd alg eb ra, m atrix m a th e m a tic s and c ro ssta lk fault.

2.1. Truth ta b le - M a tr ix M a th e m a tics M e th o d f o r (he detectio n a n d lo ca tio n o f s tr u c tu re h a za rd s in d ig ita l circu its

T ru th table - m atrix m ath e m a tic s m eth o d w as b uilt to th e d e te c tio n and lo ca tio n h azard s in c o m b in a tio n a l circu its th a t is e x p re sse d in e ith e r sum -of- p ro d u c ts (S O P ) form o r p ro d u ct-o f-su m s (P O S ) fo rm o r both. T h e m ain idea o f this w o rk IS to “d ip ” th e v a ria b les o f fim c iio n on th e ir truth ta b le b y m u ltip ly in g th ese m a tric e s c o n fo m i to the rules o f m u ltip lic a tio n m atrix (m a th em a tic s). T h e result o f th e m u ltip lic a tio n is c o m p a red w ith d efin itio n s o f hazard s in h a z ard alg eb ra [1], [2], [3]. T h at is ^ =

^ (0 ) as static 0 - hazard, ^ ^ t ” -r ^ (1) as sta tic I - h a z a r d aruli^ ^ x’ ^o(O) , ^ ^ ( t^ + = ^ e (l) as d y n a m ic h a z ard d ep e n d en t on static 0- h a z ard and d y n a m ic h a z ard d e p e n d en t on sta tic 1- h a z ard , resp ectiv ely .

T h e p rin c ip le o f th is m eth o d as follow s: firstly w e find the v ariab les X th a t can c a u se hazard , and th e n fix v alu e 0 or 1 in v a ria b le s Xj X. T o realize th is p roblem w e can “d ip ” th e v a ria b le s, the sum fac to rs o r the p ro d u ct term s o f c irc u it eq u a tio n on th e tru th tab le n v a ria b le s b a se d on m u ltip ly in g eq u a tio n - m a trix w ith truth ta b le - m a trix that c o n fo rm to th e m le s o f m u ltip lic a tio n m atrix (m a th em a tic s).

T h e e q u a tio n ~ m a trix is a m atrix ex p re ss circu it eq u atio n . I f c irc u it e q u a tio n in fo rm SO P, th en c irc u it e q u a tio n w ill h o ld s su m fac to rs and i f circuit eq u atio n in form P O S , th en c irc u it eq u atio n w ill h o ld s p ro d u c t term s. N u m b e r o f sum fac to rs or p ro d u ct te n n s in th ese c irc u it e q u a tio n s sh o w s n u m b er colu m ns o f m atnx, that is, matrix with dim ensions Ixn that IS matrix w ith 1 row and n colum ns.

T h e M a trix truth ta b le is a m atrix ex p ress ưxith tab le o f c irc u it fu n ctio n . In th is m eth o d the fruth ta b le is re p u te d to be a m atrix n X 2""', it m ean s m atrix w ith n c o lu m n s an d 2 " “ ‘ ro w s.

T o m ak e n u m b e r o f c o lu m n s in c irc u it eq u atio n - m atrix equal to n u m b e r o f ro w s in tru th table - matrix w e can change this matrix into transpose matrix, that is, let A be an n X 2" ' matrix defined by th e n u m b e r aịj, then th e tra n sp o se o f A as A^, d en o ted is the 2"'' X n m a trix d e fin e d b y the n u m b er

bjj where bji =

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N.Q. Thuong / VNU Journal o f Science, Mathematics - Physics 27(2011) 123-130 125

T he algorithm to d e te c t stru ctu re h azard s m com b in atio n al c irc u it o f th is m eth o d IS g iven as follow s:

S tep 1: C o n sid e r the c irc u it eq u atio n .

I f the c irc u it eq u a tio n is c o m p lic a ted , then apply D e M o rg an L aw to get the sim plest c irc u it eq uation that are circuit e q u a tio n s in form s e ith e r SO P or PO S or both.

S tep 2: C o n sid e r the variab les. _

- F irstly, find the v a n a b le s that can cause hazards. T hey are th o se variab les h av in g b o th X a n d X form , in this case x:= x " a n d x ’:= x' are independent.

Fix X ) v a lu e s (0 ,1) b y “d ip ” c irc u it eq uation n v a ria b le s on th e tru th table o f c irc u it function resp ectiv ely that re a liz e d b y m u ltip ly in g tw o m atrices that are circu it eq u a tio n - m a trix an d truth table - m atrix.

S tep Ỉ: C o n sid e r the re s u lt o f m u ltip lic a tio n

A fter the variablesX are fixed value 0 or 1 by “ d ip ” circu it eq u a tio n n v ariables o n th e tru th table so we get the resu lt o f m u ltip lic a tio n th at eith e r the sum facto rs t ” . t ’’ = ^ (0), the c irc u it con ta in s static - 0 hazard, or the product term s t" + t ‘- = ^ (1), that IS the circuit co n ta in s static - 1 hazard, or dynam ic hazard dependent on static logic 0 - hazard

Ị,

= t". x‘' = ^o(O) and dynam ic h a z ard d ep e n d en t on static logic 1 - h azard ^ = (x"+ ) .t " = 4o (l). o r n o t at all, th at is the free h a z a rd circuit.

S tep 4: In v estig ate to re m a in in g v ariab les

T o find the rem a in in g v a ria b le s X jthat can cause hazards. G o to Step 2, S tep 3 until last v a ria b le Xi is co n sidered.

2.2 To d etec t cro ssta lk f a u l t in d u c e d fu n c tio n h a zards

A fter the digital circu it is d e sig n e d an d b u ilt, it is alw ays d esirab le to k n o w w h e th e r the c irc u it is c o n sừ u c te d w ith o u t any faults. Is it IS p ro p erly co n stru c te d and in use, it m ay be d isa b le b y a lm o st an y internal failure. T h e p ro ce ss o f a p p ly in g te st an d d eterm in in g w h e th e r a digital c irc u it is fault free o r n o t is know n as fault d ete c tio n . I f w e k n o w n rela tio n sh ip ex ists b e tw e en the v a rio u s possib le fau lts and d ev iatio n s o f outp u t p a tte rn s, IS term ed as fault lo cation [12] as fu n c tio n ha za rd . T h e in c re a se d d e sig n d en sity in deep - su b m ic ro n d e sig n s leads to m ore sig n ifican t in te rfe re n c e b e tw e e n the sig n a ls b ecau se o f c a p ac itiv e c o u p lin g o r cro sstalk . C ro ssta lk can induce b o th B o o le a n e ư o r s and delay fau lts.

C ro ssta lk - in d u ced p u lses are lik e ly to cause errors on h a z ard - sen sitiv e lines such as in p u ts to d y n am ic g ates, clock, se t/re se t an d d ata in p u ts to flip - flops. C ro ssta lk p u lse s m ig h t resu lt in lo g ic e ư o r s o r d eg rad ed vo ltag e lev els, w h ic h increase p ro p ag atio n d elay s [6].

Studies sh o w that in cre ase d c o u p lin g e ffe c ts b etw een signals ca n cau se sig n a l d e la y to in c re a se (slo w dow n) or d ec re a se (sp e e d up) sig n ifican tly . B oth c o n d itio n s can cau se errors. S ignal slo w d o w n can cause delay fa u lts if a transition is propagated along paths with small slacks. Signal speed - up can c a u se race (glitch) c o n d itio n s i f a tra n sitio n s are pro p ag ated a lo n g short p a th s [6], C ro sstalk g litch o c c u rs w hen th ere is a sw itch for th e signal at o n e line and the signal at the o th e r line is d riven ste a d y , in w h ic h case a g litch is fo rm ed at th e o u tp u t o f the steady line. T h e co n d itio n fo r c ro sstalk d e la y is th at the signal at b o th line sw itc h e s to the op p o site d irection. T h e re su lt is an in cre ase in fra n sitio n tim e [5]. F o r tw o line in a circ u it, i f the signal ữ a n sitio n o f 0 to 1 o r 1 to 0 o n a line p ro d u ce s c o u p lin g e ffe c ts on a n o th e r line, th en th e signal line is called an a g g re sso r line, an d th e o th e r line is c a lle d a v ic tim line. F o r in stan ce, i f th e v ic tim line an d a g g re sso r line are d riv e n re sp e c tiv e ly b y a static 0 a n d a

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N.Q. Thuong / VNU Journal o f Science, Mathematics - Physics 27 (20Ỉ I) 123-130

fast - rising ( 0 to 1) tra n sitio n , then the cro sstalk p o sitiv e g litch is g e n e ra te d in th e v ic tim ’s ou tp u t s ig n a l. I f the heig h t o f c ro sstalk g litc h h ap p en s to be larg er than the u p p e r - th re s h o ld v a lu e o f logic - lo w voltage for the g ive tec h n o lo g y , it w ill p ro d u ce logic failures fu n c tio n a lity p r o b le m ) [6], W e c o n s id e r the function h azard in dig ital circuit, w as p u t into use, as d e te c t the c ro s s ta lk faults. H ere w e d e fin e cro sstalk fault on digital c irc u its b y u sing B in a ry D e c isio n D ia g ra m (B D D ) o f [6],

So i f w e w ant to d ete c t all fo rm s o f h a z ard in the circu it so, th en w e n eed to d e te rm in e structure h a z a rd s w ithin the desig n p ro cess and fu nction h azard by d e te rm in in g the cro sstalk fau lt.

3. D etection structure hazard in com binational circuits

F ro m d efin itio n s o f h azard and the alg o rith m to d etect h azard o f th is m eth o d in se c tio n 2 n ow w e ca n fin d hazard s in circu its fo r su m - o f - p ro d u cts im p lem e n ta tio n , or for p ro d u c t - o f - sum s im p lem e n ta tio n , or c o m p lic a ted c irc u it th at is not o n ly in forni P O S o r S O P b u t a lso h o ld all PO S and S O P . L et us c o n sid er an E X - O R g ate [9] (Fig. 5) as co m plex circu it

X --- ---

w

Y Q

Fig. 1. Circuit with EX - OR gate.

S te p 1: F rom this circu it w e have c irc u it equation:

Q = X Y + X Y + X + W + X Y + X Y + Z U se the B o olean rela tio n s to c h an g e circu it equation, w e get:

Q - + XỸ)X w +

(X

+ Y)(X + Y)Z

S te p 2: T he C ircuit eq u a tio n has tw o variab les X ( x ^ ',T ^ ) and Y ca n c a u se hazard.

F irstly , c o n sid e r for X:

X : =

(Y,Z,W): = (OJ) ^

T h e eq u atio n Q h as tw o su m fa c to r s that are (XY + XY )X W and (X + Y )(X + Y )Z (in form SO P), b u t in one sum facto r h o ld p ro d u ct term s (PO S). E xam ple: sum fa c to r (3Õ" +

XỸ)XW

hold tw o p ro d u c t term s (X Y + X Y ) an d x w (PO S and SO P). So w e C a n cre a te from c irc u it e q u a tio n Q to one m afrix M w ith tw o p ro d u c t term s (X Y + X Y ) , X

w

and one sum fac to r (X + Y )(X + Y )Z

‘ 0 1 0 1 0 1 0 1

M.A^ =[(3Ò^ + XỸ) (XW) (X + Y)(X + Y ) z ] . 0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

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N.Q- T h uong/ VNU Journal o f Science, Mathematics - Physics 27 (20Ĩ1) Ỉ23-Ỉ30 127

Also re s u lt o f m u ltip lic a tio n in a co lu m n is d efin ed b y ad d itio n (A o C ) for sum fac to rs an d m u ltip ly (M oC ) for p ro d u c t term s. E x am p le, resu lt o f m u ltip licatio n in first c o lu m n o f b e lo w M .A is

). . So w e get:

M .A ^ = ( t " )

_L

(T ^ )

L

(x«)

(0) L

(T^) (t^^)

II L ^ L L L

(t ) + t: (t ) . (t ) + t t

(0)

xL L

0

I]

( x » ) ( t ^ ) Y

(0) (0)

z

0 0

w

- 1

Y = 0 Y=1 Y - 1

z =0

ệ ( l ) i n ^

z =0

^(0) in -

z= 0

0

w =0 w =0 W=1

C o m p are w ith D e fin itio n 1 and 2 w e find out one static - 0 h azard ậ (0 ) in

Y - w

- 1,

z

- 0, one static - 1 h a z a rd ^ ( l ) i n Y = Z = W = 0 and one dynam ic h a z ard d e p e n d e n t static - 1 h azard ^0 (1) in Y =

l,z =

w = 0.

Step 4: G o to Step 2, S tep 3 to c o n sid e r variable Y : Y ; = (T»,x^)

(X,Z,W): = (0,1)

0 1 0 1 0 1 0 1

M . A ' = [ M 0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

u u

1( t “ ) ( x “ )

(x") (T*-)

( x ^ - ) (t'-) (x^-) X

- ( t " ) ( x " ) (0) ( 0 ) (t“ ) ( t " ) (0) (0)

z

0 T*- 0

0 0 w

0 (t» )(:-'■)+r ' - ( T ” ) ( r ^ ) 0

0

u Ji u

x =0 x - 0 X=1

^ ( l ) i n <

z = 0 ệ (0)

in

0

z =0 m

in

■z =0

w =0

W =1 W = 1

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N.Q. Thuong / VNU Journal o f Science, Mathematics - Physics 27 (2011) 123-130

w e have id entified h a z a rd s ^ (1)

e Ị x = Z = W = o Ị ,

^ (0)

e í X = W = l , Z = 0 ) Ị

and

^Q(0)e(x = l, z = w = 0)

T h u s, the circuit fu n ctio n Q has n o t only dynam ic h a z ard [9], b u t a lso sta tic - 1 h a z a rd and static -

0 hazard .

4. D etection C rosstalk induced function hazard

T o determ ine th e g litch in the circu it than w e n eed to id en tify th e c ro s s ta lk fa u lt. In p rin c ip le to d e te rm in e the stuck a t fault o r cro sstalk fault is to create the test v e c to r. I f th e re I S a fa u lt in a circuit th e n the test v ectors o f the fau lt are the input assig n m en ts th at cau se th e fa u lty c irc u it and norm al c irc u it (fault - free c irc u it) to p ro d u ce d iffe re n t ou tp u t values. T h e test v e c to r d is tin g u is h b etw een the g o o d m ac h in e and th e fau lted m ach in e. So the test v e c to r is bu ilt, w h ic h is th e X O R o p e ra tio n o f the fa u lt - free circuit an d faulty circu it. F igures 2 [10] tells us m ore a b o u t th is in F u n c tio n a l E qu iv alen ce a n d F u n c tio n a l D o m in an ce (F u n c tio n a l C o llapsing): F o r an in p u t v e c to r, V , to b e a te st fo r a fault, we h ave:

F , ( V ) 0 F , ( V ) = 1

w h e re Fo is the fault - free fu n ctio n and F | is the faulty fun ctio n , re s p e c tiv e ly . C o n s id e r a second fault th a t p ro d u c e s a fault fu n ctio n p2. A c c o rd in g lo the defin itio n o f fau lt e q u iv a le n t fa u lts h a v e ex actly the sa m e tests. T h erefo re, for tw o fau lts to be eq u iv alen t, w e have

[F„ ( V ) © F, (V )]

e

F, (V )] = 0 => F, (V )] © R ( V ) = 0

Fig. 2. \ ’iewing fault Equivalence.

In [6] te st v ecto r is ca lled test B D D (T e st B in ary D e c isio n D ia g ra m ), n o rm a l c irc u it a re know n as n o rm a l B D D an d fau lty c irc u it is fau lty B D D , so w e h av e test B D D ;

T e st B D D = n o rm al B D D • faulty B D D + n o rm al B D D • fa u lty B D D =1 In th e te st B D D , e a c h in p u t assig n m en t w ith attrib u te valu e 1 is a te st v e c to r o f th e fau lt.

T h e cro sstalk fau lt is o n e o f th e in te rfe re n c e effects b e in g c a u se d b y p a ra s itic c a p a c ita n c e and in d u c ta n c e coupling. F o r tw o lin e in circu it, i f the signal tra n sit o f 0 to 1 o r 1 to 0 o n e lin e produces c o u p lin g e ffe c ts on a n o th e r line, then the line is called an a g g re sso r lin e, th e o th e r I S c a lle d a victim line. F ig u re 3 show s th e re la tio n sh ip b e tw e en a g g resso r line an d v ic tim lin e [1 1 ].

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N.Q. Thuong / VNU Journal o f Science, Mathematics ~ Physics 27 (201Ỉ) 123 -Ỉ 30 129

Y1 Y1 Y i Y1

Yi-1 Yi-1 Yi-1 Yi-1

victim Y1 0 victim

Y i Y 1 victim

Y1

Yi+I Yi+1 Yi+1 Yi+1

Yn Yn Yn Yn

victim

i

A

victim

V

i

victim victim

victim

Positive glitch Negative glitch Slow to fall

Fig. 3. Maximal aggressor fault model.

Slow to rise

T he P o sitiv e g litc h a n d N e g a tiv e g litch in Fig. 3 are fu nction h azard s. T h e se H a z a rd s can n o t be rem oved d u rin g th e d e s ig n p ro c e ss, b e c au se th ey a p p e ar only a fte r hav in g tak e n in to use.

H ere fo r c irc u it C 1 7 [6 ] sh o w n in Fig. 4, w e give an e x am p le for test g e n e ra tio n w hen th ere is a cro sstalk fau lt b e tw e e n s ig n a l lin e s C3 and C4. T h e task o t test g e n e ra tio n is to se a rc h for the in p u ts v ectors o f c irc u it c 17 in o rd e r to d e te c t the c ro sstalk fault. F or ex am p le, a te st v e c to r o f the c ro s s ta lk fault is made up o f circuit input vectors Vi = (Xi, X 2 , X 3 , X 4 , X 5 ) = (0, 0, 0, 0, 0) and V2 = (X|, X2, X3, X 4 ,

X5) = (0, 0, 0, 0, 1). A p p ly V i and V2 to the circuit seq uentially. I f the c irc u it o u tp u ts are yi = 0 a n d y i

= 0 for V i, y , = 0 a n d y2 = 1 for V2., th en th ere is not crosstalk. I f th e c irc u it o u tp u ts are yi = 0 a n d yz = 0 for V ,, y, = 1 a n d y2 = 1 for V2,, th en there is crosstalk. T h e refo re, th is te s t v e c to r ca n d e te c t th e cro sstalk fa u lt b e tw e e n 6 3 a n d 6 4 . H ere, assu m e that C4ÌS a a g g re sso r line an d 6 3 is a victim lin e , an d th at a d o w n tra n s itio n (1 to 0 ) in sig n al line 6 4 pro d u ces a g litch (1 to 0) in signal lin e e3, th a t is, th e re is a function h a z ard .

ei

X I

X3 X2

X4

X5

6 2

G3

y i

o-

y2

6 4

Fig. 4. C17 Cừcuit.

(8)

130 N.Q. T h u o n g / VNU Journal o f Science, M athem atics - Physics 27 ( 2 0 ỈĨ ) Ỉ2 3 -Ỉ3 0

5, C onclusion

T h e d etectio n , lo c a te a n d re m o v e th e H a z a rd s o f th e d ig ita l c irc u its is v e ry c ritic a l fo r circuit d e sig n e rs. S tru ctu re h a z a rd a re d e te c te d a n d re m o v e d e v e n d u rin g th e d e s ig n p r o c e s s an d th e re w ere s o m e m e th o d s to s o lv e th is. T r u th ta b le - M a trix M a th e m a tic s M e th o d p re s e n te d h e re is a new s o lu tio n to in v e stig a te s tru c tu re h a z a rd . T h is m e th o d n o t o n ly d e te c te d all k in d s h a z ard s in combinational circuits but also point out location o f hazards w ith high accuracy. The Truth table - M a trix M a th e m atic s c a n d e te c t h a z a rd in all c irc u it fu n c tio n s th a t c a n e x p re s s e d b y tru th table. T he re m o v in g stru c tu re h a z a r d e rro rs n o d iffic u lty i f w e u se K a rn a u g h m a p [8] o r h a z a rd a lg e b ra [1-3] to s u p p ly red u n d a n t te rm s c o rr e s p o n d in g e a c h k in d o f h a z a rd . T h e s e fu n c tio n h a z a rd c a n n o t b e rem o v ed d u rin g th e d e sig n p ro c e s s , b e c a u s e th e y a p p e a r o n ly a fte r h a v in g ta k e n in to u se . D u ra tio n o f function h a z a rd can p e rm a n e n t, te m p o ra ry o r in te rm itte n t, th u s re m o v in g it is n o t e a sy . W e can determ in e fu n c tio n hazard, fo r e x a m p le th ro u g h th e id e n tific a tio n o f c ro s s ta lk f a u lt a s d e s c rib e d a b o v e .

R eferen ces

[1] John Knight, A synchronous Circuits Races Cycles, a nd Effect o f Hazards, Electronics D epartm ent Carleton University, April 1, 2006,

[2]N .Q . Thuong, Race and hazard algebra in asynchronous system, K//Ơ Jo u rn a l o f Science, Mathematics- Physics, VoL24, N o .l (2008) 47.

[3] John Knight, Glitches a nd H azards in D igital Circuits, Electronics D epartm ent, Carĩeton U niversity April 1, 2006.

[4] Shehzad Hasan (advisor: Prof. w . A nheier) (hasan, anheier), Test Pattern Generation a nd Compaction fo r Crosstalk induced Gỉitch Fault, ITEM , University o f Brem en, Otto - H ahn - Allee 1, 28359 Bremen, Germany.

[5] Xiaoyun sun, seonki Kim , B apiraju Vinnakoda, Crosstalk fa u lt detection by dynam ic Idd, Department of Electrical and Com puter Engineering U niversity o f M innesola, M inneapolis, M M , 55455.

[6] Zhong - Liang Pan, Ling Chen, G uang - Zhao Zhang, Cultural A lgorithm for M inim ization o f Binary Decision Diagram and its A pplication in Crosstalk Fault D etection, International Journal o f Automation and Computing, 7(1) February (2010) 70.

[7] Kwang - Ting Cheng, C urrent D irections in Autom atic Test - Pattern Generation^ U niversity o f California, Santa Barbara.

[8] M. Karnaugh, A M ap M ethod for synthesis o f com binational logic circuit, Transactions o f the AỈEE, Communications a n d Electronics, V ol72:l (1953) 593.

[9] E .c . Tan, M.H. Ho, M atrix m ethod to detect logic hazard in com binational circuit w ith EX OR gate, Journal o f Universal Com puter Science, vol. 5, 11 (1999) 765.

[10] Raja K. K. R. Sandừeddy, V ishw anti D. A grawal, D iagnostic a n d D etection F ault CoUapsing fo r Multiple Output Circuits, D epartm ent o f Electrical and Com puter Engineering A uburn U niversity, AL 36849, USA.

[11] Jin Fu Li, Transistor Stuck - Open Fault, A dvanced Reliable system s (A RES) Lab.

[12] Thamarai, S.M. K uppusam y, K. M eyyappan, T. Enhancing test pattern com pacrion algorithm s for simple two stage cừcuits, International Journal o f Current Research, v.)l. 4 (2010) 015.

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