Hội nghị Quốc gia về Điện tử - Truyền thông

REV 2013

KỶ YẾU

Hội nghị Quốc gia về Điện tử - Truyền thông

Hà Nội, ngày 17-18/12/2013

ĐẠI CÔNGHỌC

NGHỆ ĐẠI CÔNGHỌC

NGHỆ

Chào mừng kỷ niệm 25 năm thành lập Hội Vô tuyến Điện tử Việt Nam Hội Vô tuyến Điện tử Việt Nam

Chương trình Khoa học Công nghệ trọng điểm cấp Nhà nước KC01 Trường Đại học Công nghệ, Đại học Quốc gia Hà Nội

Nhà xuất bản Đại học Quốc Gia Hà Nội

KC01

A T C / R E V 2 0 1 4

O c t o b e r 1 5 – 1 7 , 2 0 1 4

The International Conference on Advanced Technologies for Communications (ATC/REV) is an annual conference series, co-organized by the Radio Electronics Association of Vietnam (REV) and the IEEE Communications Society (IEEE ComSoc). The goal of the series is twofold: to foster an international forum for scientific and technological exchange among Vietnamese and worldwide scientists and engineers in the fields of electronics, communications and related areas, and to gather their high-quality research contributions.

Started in 2008 in Hanoi, the conference has made a great tour across Vietnam, for better promoting its scientific development (2009 - Haiphong, 2010 – Ho Chi Minh City, 2011 - Danang, 2012 – Hanoi, 2013 – Ho Chi Minh City). We now invite you to return to Hanoi city for the 7th meeting – the ATC/REV 2014 – to be held during October 15–17, 2014, and hosted by Posts and Telecommunications Institute of Technology.

TECHNICAL PROGRAM

The conference program includes the regular tracks and special sessions spread over three days. In addition, a number of tutorial sessions will be scheduled on the day before the conference starts. Authors are invited to submit original unpublished papers. Topics of interest include but are not limited to:

Communications track

 Communication Theory

 Information & Coding Theory

 Communication Quality, Reliability & Modeling

 Communications & Information Security

 Wireless Communications

 Optical Communication & Networking Microwave & Antennas track

 Antennas & Propagation

 Microwave Theory & Techniques

 RF, Microwave Systems and Applications

Networks track

 Ad Hoc & Sensor Networks

 Computer Communications

 Satellite Communications

 Network Operations & Management

 Communication Switching & Routing

 Emergency Communications Biomedical Engineering

 Bio-signal processing

 Telemedicine and E-hospital

 Biomechanics

Electronics track

 Analog and Mixed-Signal Circuits

 Embedded Systems, IP & Systems Design

 Synthesis, Optimization, Verification & Testing

 Consumer and Multimedia Systems

 Circuits and Systems for Communications

Signal Processing track

 Signal and Image Processing

 Speech and Video Processing

 Signal Processing for Communications

SUBMISSION & POLICIES

IMPORTANT DATES

All papers must be submitted electronically, in PDF format, and uploaded on EDAS. The direct link for paper submission is at http://edas.info/N16379. The submissions should be formatted with single-spaced, double-column pages using at least 10 pt (or higher) size fonts on A4 or letter pages in IEEE style format. Detailed formatting and submission instructions will be available on the conference web site (http://www.rev-conf.org/authors/submission-guidelines.html).

Submitted papers (for both regular and special sessions) are subject to a blind review process handled by an international technical program committee. An author of an accepted paper must be registered at full rate (member or non-member of the IEEE or REV) prior to uploading the camera-ready version. The maximum length of the camera-ready version is 6 pages. Accepted and presented papers will be included in the IEEE Xplore Digital Library. The IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference.

Regular/special paper submission:

Manuscript submission: April 30, 2014 Notification of acceptance: Jul. 30, 2014 Camera-ready submission: Aug. 30, 2014 Proposal submission:

Special sessions: Mar. 1, 2014

Tutorials: Mar. 1, 2014

COMMITTEES INTERNATIONAL LIAISONS

Honorary chairs

Nguyen Van Ngo, REV, Honorary President Do Trung Ta, KC.01 Program, VN Steering chairs

Phan Anh, Bac Ha International Univ., REV Vijay Bhargava, UBC, Canada, ComSoc Hoang Minh, Posts & Telecom. Inst. Tech., VN General chairs

Robert W. Heath, The Uni. Texas at Austin, US Nguyen Xuan Quynh, REV, VN

Le Huu Lap, Posts & Telecom. Inst. Tech., VN Plenary talks

Huynh Huu Tue, VNU-HCM, VN Local arrangements

Vu Tuan Lam, Posts & Telecom. Inst. Tech., VN Finance

Nguyen Minh Phuong, Posts & Telecom. Inst. Tech., VN Publicity

Nguyen Trung Kien, Posts & Telecom. Inst. Tech., VN Industrial relations

Dang Hoai Bac, Posts & Telecom. Inst. Tech., VN Publication

Le Nhat Thang, Posts & Telecom. Inst. Tech., VN Tran Xuan Tu, VNU-HN, VN

Technical program chairs

Arumugam Nallanathan, King's College London, UK Trung Q. Duong, Queen’s University Belfast, UK Vo Nguyen Quoc Bao, Posts & Telecom. Inst. Tech., VN

America

Jean-Yves Chouinard, ULaval, Canada Minh Do, UIUC, USA

Robert Heath, The Uni. Texas at Austin, USA Tho Le-Ngoc, McGill, Canada

Ha H. Nguyen, Univ. Saskatchewan, Canada Asia

Fawnizu A. Hussin, UTP, Malaysia Yoshio Karasawa, UEC, Japan Bumman Kim, POSTECH, South Korea Beyong Lee, SNU, South Korea Fujino Tadashi, UEC, Japan Wenxun Zhang, SEU, China Australia & the Pacific Eryk Dutkiewicz, MQ, Australia Dinh-Thong Nguyen, UTS, Australia Middle-East & Africa

Boualem Boashash, QU, Qatar Europe

Maurice Bellanger, CNAM, France Merouane Debbah, SUPELEC, France Pierre Duhamel, L2S/SUPELEC, France Yacine Ghamri-Doudane, ENSIIE, France Peter Müller, IBM Zurich, Switzerland Matthias Pätzold, UiA, Norway Zebo Peng, LiU, Sweden

Roberto Saracco, Telecom Italia, Italy

CALL FOR PAPER

REV Journal on Electronics and Communications (REV-JEC) is a quarterly peer-reviewed research journal, dedicated to providing a leading edge forum for researchers and professionals to contribute and disseminate innovative research ideas and results in the fields of electronics and communications.

REV-JEC offers three different formats of articles: regular, short and correspondence. While it is required for a regular article to present substantial scientific contributions in sufficient details; a short article should present a complete study with significant contributions, usually more limited in scope than what is found in a regular article; and a correspondence article may offer new ideas, new results or comments that need to be quickly communicated.

We invite submission of high-quality papers presenting original, previously unpublished, research ideas and results on both theoretical and applied aspects in all areas of electronics and communications. These areas include, but are not limited to, the following topics:

Automation and Control track

 Automation Systems

 Adaptive Control

 Linear & Nonlinear Control

 Optimal Control

 Robotics Communications track

 Communication Theory

 Information & Coding Theory

 Communication Quality, Reliability &

Modeling

 Communications & Information Security

 Wireless Communications Electronics track

 Analog & Mixed-Signal Circuits

 Embedded Systems, IP & Systems Design

 Synthesis, Optimization, Verification &

Testing

 Consumer & Multimedia Systems

 Circuits & Systems for Communications

Microwave & Antennas track

 Antennas & Propagation

 Microwave Theory & Techniques

 RF, Microwave Systems & Applications Networks track

 Ad Hoc & Sensor Networks

 Computer Communications

 Internet

 Optical Networking

 Satellite Communications

 High-Speed Networking

 Network Operations & Management

 Communication Switching & Routing

 Emergency Communications Signal Processing track

 Signal Processing Theory

 Audio & Acoustic Signal Processing

 Image & Video Signal Processing & Coding

 Speech Processing

 Biomedical Signal Processing & Imaging

 Signal Processing for Communications &

Networking

 Information Forensics & Security

 Signal Processing Applications & Systems Manuscripts should be written in English. Whenever applicable, submissions should include the following elements: title, authors, affiliations, contacts, abstract, index terms, main text, acknowledgement, and references. Submitted manuscripts should be formatted into A4-size, double- spaced, single-column pages, with main text of 12-point type. Regular research paper submissions should ideally not exceed 30 double-spaced pages in length, including tables and figures. This length corresponds roughly to 7 pages in print (single-spaced, two-column format). Prospective authors should submit their full-text manuscript for publication consideration in a single PDF or Microsoft Word file via email to the journal secretary at jec@rev.org.vn. Other file formats will not be accepted.

Office: G2 building, 144 Xuan Thuy, Hanoi, Vietnam

Phone: +84 4 37549271 – Email: jec@rev.org.vn – Website: http://www.rev-jec.org

REV 2013

HỘI NGHỊ QUỐC GIA VỀ ĐIỆN TỬ - TRUYỀN THÔNG NATIONAL CONFERENCE

ON ELECTRONICS AND COMMUNICATIONS

Kỷ yếu hội nghị

ĐIỆN TỬ - TRUYỀN THÔNG

VỚI CÁC NGÀNH CÔNG NGHỆ CAO

17 – 18 tháng 12, 2013 Hà Nội

Đơn vị tổ chức Đơn vị tài trợ

ĐẠI CÔNGHỌC

NGHỆ ĐẠI CÔNGHỌC

NGHỆ

KC01

ii

Hội nghị Quốc gia về

Điện tử - Truyền thông với Các ngành công nghệ cao 2013

Ban chỉ đạo ________________________________________________________ vi Ban tổ chức ________________________________________________________ vii Ban chương trình và Ban thư ký ______________________________________ viii

Báo cáo mời

Xu hướng phát triển và định hướng quy hoạch tần số cho vô tuyến băng rộng của Việt Nam __________ 1 Ths. Đoàn Quang Hoan

Một số chính sách mới của khoa học và công nghệ cho phát triển lĩnh vực công nghệ thông tin và truyền thông _________________________________________________________________________ 2

PGS.TS. Đào Ngọc Chiến

Chính sách, chiến lược, xu hướng phát triển và điều tiết thị trường Viễn thông và Công nghệ thông tin Việt Nam __________________________________________________________________________ 3

PGS.TS. Trần Minh Tuấn

Hội Vô tuyến Điện tử Việt Nam với các hoạt động nhằm thúc đẩy sự phát triển của Khoa học - Công nghệ Việt Nam trong lĩnh vực Điện tử và Truyền thông _______________________________________ 4

GS.TSKH. Phan Anh

Relations of Friendship and Cooperation between the IEEE and the Radio-Electronics Association of Vietnam ____________________________________________________________________________ 9

Prof. Nguyen Van Ngo

Báo cáo tại các phiên

Đánh giá hiệu năng giao thức cây thu thập dữ liệu có sự nhận thức về năng lượng _________________ 19

Vũ Chiến Thắng, Nguyễn Chấn Hùng, Lê Nhật Thăng

Giải pháp bảo mật và xác thực cho văn phòng điện tử _______________________________________ 26 Hồ Văn Hương, Hoàng Chiến Thắng, Nguyễn Quốc Uy

Implementing Rate Adaptive Algorithm in EnergyAware Data Center Network ___________________ 32 Tran Manh Nam, Tran Hoang Vu, Vu Quang Trong, Nguyen Huu Thanh, Pham Ngoc Nam

Nghiên cứu khắc phục ảnh hưởng của trễ truyền thông trong các hệ thống điều khiển có nối mạng ____ 38 Nguyễn Trọng Các, Nguyễn Văn Khang

A Low Offset Op-Amp Using Auto-zero and Ping-pong Structure ________________________ 47

Tan-Vinh Le, Binh-Son Le, Trung-Khanh Le, Trong-Tu Bui

System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder _____________ 51 Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran

Hệ thống cảm biến giọt chất lỏng trong kênh dẫn ___________________________________________ 56 Nguyễn Đắc Hải, Vũ Quốc Tuấn, Phạm Quốc Thịnh, Chử Đức Trình

Heart rate monitor and QRS detection using microcontroller __________________________________ 61 Hoang ChuDuc, Thuan NguyenDuc

Design and implementation of a watermarking method using perceptually important sub-image ______ 66 Nguyen Ngoc Minh, Nguyen Le Cuong

Designing digital filters by method of assigned transition bandwidth ___________________________ 70 Nguyen Xuan Truong

Một phương pháp xây dựng hệ mật mã khối kết hợp sơ đồ Lai-Massey với sơ đồ Feistel và ứng dụng vào hàm băm ______________________________________________________________________ 75

Ngô Đức Thiện, Nguyễn Trung Hiếu, Nguyễn Toàn Thắng, Đặng Hoài Bắc

Trích chọn đặc trưng cho bài toán nhận dạng cảm xúc bằng thuật toán Gabor Wavelet _____________ 81 Lê Đức Toàn, Nguyễn Thị Ngọc Bích, Diệp Nhật Huy, Huỳnh Hữu Thuận

Thiết kế bộ đo lường quán tính sử dụng bộ lọc Kalman mở rộng _______________________________ 88 Nguyễn Quang Vịnh, Trần Xuân Kiên, Bùi Hông Huế

Hệ thống mạng camera xử lý hình ảnh thông minh phục vụ điều khiển giao thông và giám sát an ninh _ 95 Phạm Hồng Quang, Nguyễn Hữu Tình, Bùi Phú Huy, Tạ Tuấn Anh

Thiết kế lắp đặt hệ thống camera giám sát giao thông đường cao tốc ___________________________ 101 Tạ Tuấn Anh, Phạm Hồng Quang

Thiết kế, chế tạo thiết bị đo lường bức xạ ion hóa _________________________________________ 107 Nguyễn Cảnh Việt, La Minh Tuấn, Trịnh Ngọc Duy, Phạm Quốc Triệu

Development of a Behavior-based Navigation System for Mobile Robot in Unknown Environment __ 112 Thi Thanh Van Nguyen, Manh Duong Phung, Anh Viet Dang, Dinh Tuan Pham, Quang Vinh Tran

Indoor Objects Localization System Using Passive UHF – RFID Technology ___________________ 118 Thi Hao Dao, Quoc Cuong Nguyen, Minh Thuy Le

Numerical Analysis of Square/Hexagonal Photonic Crystal Fiber for Optical Fiber Communication __ 123 Nguyen Hoang Hai, Nguyen Ngoc Minh

Antenna for RFID Cards _____________________________________________________________ 130 Nguyen Minh Tran, Tran Quang Nhuong, Truong Vu Bang Giang, Tran Minh Tuan

A Novel Demultiplexer Based on a 2×2 Butterfly MMI Coupler and a Directional Coupler Using Silicon Waveguides _________________________________________________________________ 134

Cao Dung Truong, Xuan Linh Bui, Duc Han Tran, Tuan Linh Nguyen, Trung Thanh Le

Designing Wideband Microstrip Bandpass Filter for Satellite Receiver Systems _________________ 140 Tran Van Hoi, Bach Gia Duong

Đề xuất một cấu trúc anten tiểu hình cho thiết bị di động 3G _________________________________ 144

Hà Quốc Anh, Nguyễn Quốc Định, Hoàng Đình Thuyên

Low Power Wideband CMOS LNA for Digital TV Tuner ___________________________________ 148

Phat Nguyen-Tan, Cuong Huynh

iv

Simultaneous correction of random and burst errors using norm syndrome for BCH codes _________ 154 Pham Khac Hoan, Le Van Thai, Vu Son Ha

Implementation of Chaotic Pulse Width-Postion Modulation/Demodulation on PIC Microcontroller _ 159 Nguyen Xuan Quyen, Vu Van Yem

Performance of Cooperative Spectrum Sensing over Nakagami channel ________________________ 164 Viet Duc Tran, Hoang Nguyen Van, Mai Dinh Thai

An toàn mạng điều hành giám sát công nghiệp ____________________________________________ 170 Nguyễn Đào Trường, Lê Mỹ Tú, Nguyễn Ngọc Điệp

Performance Evaluation of Underlay Cooperative Cognitive Networks over Fading Channels ______ 175 Khuong Ho-Van, Tuan Dang Anh, Hung Dinh Quoc

Collaborative Relay Beamforming in Two-Way Relay Networks _____________________________ 181 Ha H. Kha, Nguyen D. Chi

Về một phương pháp đánh giá thuật toán tính RTT trong TCP theo phương pháp hàm thống kê _____ 187 Vũ Tất Thành, Nguyễn Hồng Vũ

Đề xuất anten MIMO băng thông siêu rộng ______________________________________________ 192

Lê Trọng Trung, Nguyễn Quốc Định

Một phương pháp xấp xỉ trên miền thời gian cho xung sóng khúc xạ, tán xạ trên mặt phẳng điện môi _ 196

Tiến Mạnh, Lê Vĩnh Hà

Phương pháp tính toán diện tích tấm tản nhiệt cho vi mạch khuếch đại công suất _________________ 201 Lê Đại Phong, Phạm Việt Anh, Nguy ễn Quang Huy, Phạm Cao Đại

Thiết kế và mô phỏng lưu lượng kế siêu âm đa tần _________________________________________ 205 Ngô Văn Sỹ, Hồ Anh Trang, Phạm Phan Tuyết Lê

The Design of Integrated Transceiver module for Wireless Data Communication ________________ 210 Nguyen Quang Huy, Luu Van Tuan, Le Dai Phong, Bui Quy Thang, Pham Viet Anh

Enhancing Performance of Digitized Radio over Fiber System using Optically Amplified Coherent Receiver __________________________________________________________________________ 214

Tuan Nguyen Van, Thanh-Tung Ton-That

Cân bằng nhanh bằng NƠRON ________________________________________________________ 220 Nguyễn Hoàng Linh, Lê Danh Cường, Trần Nam Trung

Sự tương đương giữa mã Cyclic cục bộ xây dựng trên nhóm nhân Cyclic và mã Cyclic truyền thống _ 225 Nguyễn Văn Trung, Nguyễn Trung Hiếu, Phạm Việt Trung

Microstrip Antenna for WLAN Applications _____________________________________________ 231 Pham Dinh Toai, Ta Dinh Duc, Truong Vu Bang Giang

Nghiên cứu đề xuất thuật toán so khớp bản đồ sử dụng cho ngành đường sắt ____________________ 234 Nguyễn Văn Nghĩa, Đỗ Việt Dũng

Cải thiện chất lượng giải mã LDPC dựa trên ma trận kiểm tra tương đương và cực tiểu trọng số của syndrome _________________________________________________________________________ 237

Nguyễn Văn Duẫn, Đỗ Quốc Trinh, Nguyễn Tùng Hưng

DPA, Một dạng tấn công SILECHANNEL hiệu quả _______________________________________ 243 Nguyễn Hồng Quang

Ứng dụng công nghệ mới trong kỹ thuật chiếu sáng tàu thủy _________________________________ 246

Trần Xuân Việt

Xây dựng công thức tính độ nhạy trong thiết kế cảm biến đo áp suất buồng đốt động cơ tên lửa _____ 250 Lê Vĩnh Hà, Phạm Quang Minh

Áp dụng lý thuyết trò chơi vào hệ thống 5G sử dụng MIMO kích thước lớn đa người dùng _________ 254 Trần Cao Quyền, Phạm Ngọc Linh

Giải pháp nhận dạng kênh vệ tinh phi tuyến sử dụng mạng nơron _____________________________ 258 Nguyễn Viết Minh, Trần Hồng Quân, Lê Nhật Thăng

Improve energy efficiency in WSN using fuzzy logic ______________________________________ 266 Ngo Van Truc, Nguyen Van Cuong

A 355W class S band compact Wilkinson combiner unit with LDMOS FET power amplifiers for wireless power transmission __________________________________________________________ 272

Chuc Doan Huu, Duong Bach Gia

Nghiên cứu ứng dụng công nghệ truyền hình lai ghép băng rộng và quảng bá HbbTV _____________ 277 Trần Nam Trung, Đinh Văn Phong

Công cụ hỗ trợ phân tích và thiết kế tế bào nhớ SRAM _____________________________________ 285 Võ Thanh Trí, Lê Bình Sơn, Bùi Trọng Tú

Một số tấn công giao thức trao đổi khóa _________________________________________________ 290 Nguyễn Ngọc Điệp, Nguyễn Quốc Toàn, Nguyễn Đào Trường

Hệ thống thu thập dữ liệu quan trắc qua mạng 3G phục vụ công tác cảnh báo lũ _________________ 295 Nguyễn Văn Đức, Đỗ Trọng Tuấn, Phạm Quốc Việt, Lê Văn Điểm

Implementation of Mobile Vehicle Monitoring System using Android Smartphone _______________ 301 Pham Tien Hung, Hoang Van Dung, Vuong Xuan Hong, Ha Duyen Trung

Multi-GNSS positioning campaign in South-East Asia _____________________________________ 307 Tung Hai Ta, Duc Minh Truong, Tu Thanh Thi Nguyen, Thuan Dinh Nguyen, Hieu Trung Tran, Gustavo Belforte

Novel MIMO Antenna Using CRLH Structure ____________________________________________ 314

Nguyen Ngoc Lan, Ho Manh Cuong, Nguyen Van Duc, Vu Van Yem

National Conference on Electronics and Communications (REV2013-KC01)

System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder

Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran SIS Laboratory, VNU University of Engineering and Technology

144 Xuan Thuy road, Hanoi, Vietnam Corresponding author’s email: tutx@vnu.edu.vn

Abstract— This paper presents an implementation of a LEON3-based System-on-Chip (SoC) testbed, which is aimed at experimentally evaluating and validating the H.264/AVC video encoding Integrated Circuit (IC) developed by SIS Laboratory at VNU University of Engineering and Technology. In addition, the paper also presents a methodology for verifying the design of H264/AVC video encoder in the Hardware/Software co- emulating fashion. The design is implemented on the DE2 development board from Altera Corporation. The testbed can help us to evaluate effectively many aspects of the developed H.264/AVC video encoder.

Keywords— SoC testbed, Harware/Software co-verification, LEON3 processor, H.264 encoder

I. INTRODUCTION

Because of the high mask set cost for fabricating ASIC (Application-specific Integrated Circuit), it is necessary to verify and evaluate carefully the design at all design phases in order to ensure the fabricated chip is without bug. Prototyping an ASIC design, which has large integration level and high complexity, using FPGA (Field Programmable Gate Array) is indispensable in the design process.

ASIC design is more and more complex. The major challenge the designer must be confronted to design such an IC (Integrated Circuit) is verification. In general, verification consumes at least 50%~80% of the design effort [1]. Verifying the design correctness is considered to be the key barrier against designing more complex VLSIs (Very Large Scale Integration), as well as exploiting leading-edge process technologies. There is not any single design tool that can solve the problem. Instead, a complex chain of tools and techniques, including classical simulation, directed and random verification, and formal techniques, etc., is required to reduce the number of design errors to an acceptable minimum. In this paper, we developed a LEON3-based System-on-Chip (SoC) testbed and the platform-based verification method, which is aimed at experimentally evaluating and validating the H.264/AVC video encoding IC designed by SIS Laboratory at the University of Engineering and Technology, Vietnam National University, Hanoi. This testbed can help us to evaluate effectively many aspects of the designed H.264/AVC video encoder.

The goal of verification is to ensure that the design meets the functional requirements as defined in the functional specification. In the top-down method for ASIC design and verification, the designers first develops a system-level model of the design from the functional specification. The system- level model is normally the high-level behavioral abstraction that is written in a high-level programming language such as C/C++. Alternatively, this model may also be created using the hardware description language (HDL) such as Verilog or VHDL. The behavioral model should be simulated in order to verify that it meets the required functionalities completely and correctly. The behavioral model is then used as a reference to refine and create a synthesizable RTL (Register Transfer Level) model.

Before being synthesized to a structural model (or gate- level model), the RTL model is verified again to ensure that it exactly provides the required functionality and performance.

The functional verification of the design at this step must be as complete and thorough as possible. This requires that the test vectors employed during simulation should provide the necessary coverage to ensure the design will meet specifications without bug. Unfortunately, the verification by simulation is difficult to test all cases. While the size of design increases, it might be unfeasible to run the full test-bench on a RTL model because of the huge simulating time. In this case, it is necessary to speed up the simulation using emulator, rapid prototype system, or hardware accelerators or to partition the design into several functional blocks. The modules are extracted from an abstract model of the design, and then individual modules can be verified independently with their associated test-bench. Afterwards, system-level emulation can run in a mixed mode where most modules are simulated with high-level abstract models, while one or some modules are substituted by hardware accelerator(s).

The rest of the paper is organized as follows. The hardware architecture of H.264/AVC video encoder is firstly introduced in Section II. Next, the design and implementation of the SoC testbed are presented in Section III. Section IV presents the methodology for verifying a hardware design by using the proposed SoC testbed. The details of validating the H.264/AVC video encoder and experimental results are presented and discussed in Section V. In Section VI, some conclusions are drawn.

51

National Conference on Electronics and Communications (REV2013-KC01)

II. INTRODUCTION TO THE H.264/AVCVIDEO ENCODER A. Basic concepts of H.264/AVC video encoding

The H.264/AVC video encoding standard is known as an efficient video encoding standard providing high quality at a very low bitrate in comparison with the previous standards such as MPEG-2 and MPEG-4.

The general architecture of the H.264/AVC encoder, composed of different functional blocks, is depicted in Fig. 1.

Fn (current)

�, F’n-1 (reference)

F’n (reconstructed)

MC

Intra prediction ME

T

Q

Q^-1

T^-1 Pre-Intra

prediction

Re-ordering

Entropy encode Blocking

Filter

FTQ

iTQ

NAL Intra

Inter

+ -

+ +

uF’n Fn

(current)

�, F’n-1 (reference)

F’n (reconstructed)

MC

Intra prediction ME

T

Q

Q^-1

T^-1 Pre-Intra

prediction

Re-ordering

Entropy encode Blocking

Filter

FTQ

iTQ

NAL Intra

Inter

+ -

+ +

uF’n

Fig. 1 Functional diagram of the H.264/AVC encoder.

In order to achieve high compression ratio, the H.264/AVC standard has adopted several advances in coding technology to remove spatial and temporal redundancies. These prominent techniques are as follows:

• A new way to handle the quantized transform coefficients has been proposed for trading-off between compression performance and video quality to meet the requirements of applications. Besides that, an efficient method called Context-Adaptive Variable Length Coding (CAVLC) is also used to encode residual data.

In this coding technique, VLC tables are switched according to already transmitted syntax elements. Since these VLC tables are specifically designed to match the corresponding image statistic, the entropy coding performance is impressively improved in comparison with schemes using only a single VLC table [2];

• The H.264/AVC adopts variable block size prediction to provide more flexibility. The intra prediction can be applied either on 4×4 blocks individually or on entire 16×16 macroblocks (MBs). There are nine different prediction modes for 4×4 blocks and four prediction modes for 16×16 blocks. After comparing among the cost functions of all possible modes, the best mode having the lowest cost is selected. On the other hand, the inter-prediction is based on a tree-structure where the motion vector and prediction can adopt various block sizes and partitions ranging from 16×16 MBs to 4×4-blocks. To identify these prediction modes, motion vectors, and partitions, the H.264/AVC specifies a very complex algorithm to derive them from their neighbors;

• The forward transform/inverse transform also operate on blocks of 4×4 pixels to match the smallest block size. The transform is still Discrete Cosine Transform

(DCT) but with some fundamental differences compared to those in previous standards [3]. In [4], the transform unit is composed of both DCT and Walsh Hadamard transforms for all prediction processes;

• The in-loop de-blocking filter in the H.264/AVC depends on the parameters so-called Boundary Strength (BS) to determine whether the current block edge should be filtered. The derivation of the BS is highly adaptive because it relies on the modes and coding conditions of the adjacent blocks.

B. VENGME Hardware Architecture

The “Video Encoder for the Next Generation Multimedia Equipment (VENGME)” project, supported by the Vietnam National University, Hanoi, aims at designing and implementing an H.264/AVC encoder targeting mobile platforms. The current design is optimized for CIF video;

however, the architecture can be extended for larger resolutions by enlarging the reference memory and the search window.

One of the factors which affect both computational path and the power consumption is the workload of the system and the data dependencies among the pipeline stages. In the H.264/AVC encoder, the most time consuming part is inter prediction including Integer Motion Estimation (IME), Fractional Motion Estimation (FME), and Motion Compensation (MC). The second time consuming module in the encoder is the Entropy Coding (EC). Therefore, the architecture should be carefully selected to improve the coding throughput and the overall performance. Our proposed designs for Intra-Prediction, Inter-Prediction, Entropy Encoder, and Forward Transformation and Quantization (FTQ) have been presented in [4]-[8].

Fig. 2 VENGME H.264/AVC encoder architecture.

The complete architecture of VENGME encoder uses a 4- stage pipeline scheme, as illustrated in Fig. 2. The first stage is used to load the data needed for the prediction. The second stage includes intra- and inter-predictions. Because FME and MC can reuse the information from IME and the data from the search window SRAM, therefore the IME and FME are merged into the same stage. Inter-prediction and intra- prediction in the same stage can be executed in parallel or separately, thanks to the system controller decision. In the

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separate mode of execution, to save the power consumption, the intra- or inter-prediction can be switch off while the other in active state. In the mixed mode of execution, the intra prediction and inter prediction can be done in parallel, the intra prediction will finish first, and its results are stored in TQIF (TQ Interface) memory. After that, the intra module can be switched off to save power. Inter prediction and motion compensation continue to find the best predicted pixels. After having inter-prediction results, TQIF memory can be invalidated to store new transformed results for inter module.

The third stage and the final stage are the same as the classical 4-pipeline architecture. The complete VENGME architecture has been implemented using a CMOS 0.18µm technology from ams AG.

III. D^{ESIGN AND} IMPLEMENTATION OF A S^OCT^ESTBED The top-level architecture of the SoC testbed is shown in Fig. 3. Altera DE2 development board is used as a prototype for this SoC testbed. The SoC testbed mainly consists of the blocks as follows. LEON3 processor [9] functions as the central processing unit (CPU) that takes charge of managing and scheduling all activities of the system. It receives the interrupt, stores data from input devices, processes data, and sets up operations for data transfer between memory and other devices. A real-time operating system (RTOS) (e.g., Linux) running on the processor may be responsible for performing all the above tasks. SDcard/SDRAM/FLASH/SRAM controllers provide the interface to external SDcard/SDRAM/FLASH/

SRAM memories, respectively. SD card stores benchmark video sequences. SDRAM (Synchronous Dynamic Random Access Memory) buffers input data (e.g., the encoding video frame) and intermediate data (e.g., reference frames and encoded frames). SRAM (Static RAM) buffers the temporary data during operating of the system. Flash memory stores the initialization and configuration information of the system, as well as holds the application program for CPU. The components communicate with each other by an AMBA bus, which is an on-chip bus architecture defined by ARM. The AMBA bus consists of three parts: AMBA High-performance bus (AHB) aims at connecting to high-bandwidth devices;

AMBA peripheral bus (APB) targets at connecting to the devices that require a lower bandwidth; and a bridge joins AHB bus and APB bus together (AHB/APB Bridge). Some assistant functional modules such as interrupt controller (IRQ controller), UART, Timer, PS/2 and GPIO interface are connected to APB bus, whereas SDRAM/FLASH/SRAM controllers are connected to AHB bus.

User-defined IP (Intellectual Property) cores can be connected to AHB or APB bus for verifying. For example, considering the H.264/AVC encoder that organized into a number of modules (i.e., User-defined IP core in Fig. 3). Each IP core is specific to a particular function such as ME, DCT, etc. To increase the flexibility, we have developed a wrapper that make the interface of IP core compatible with the AHB or APB bus so that it can communicate with other integrated components in the system. The wrapper integrates a PLL (Phase Lock Loop) and a DMA (Direct Memory Access) unit,

which are reprogrammable at run-time by CPU. Here, PLL takes charge of synthesizing the clock signal that required by IP core, whereas DMA unit is responsible for getting and putting the data from and to SDRAM memory during IP core operation.

Fig. 3. Top-level architecture of SoC testbed.

IV. VALIDATION METHODOLOGY

The system-on-a-chip (SoC) design and verification flow is shown in Fig. 4. In SoC design methodology, system-level design is implemented after the system specification was defined. A high-level description of application/algorithm is developed, which describes the architecture of the design by using the C language (so called C-Model) for simulating and analyzing different parameters of target system architecture, as well as verifying the design against the functional requirements.

Description of Application/Algorithm in C Language (e.g. C-Model)

HW/SW Partition

YES

Emulator for HW/SW co-verification HARWARE DESIGN

Profile

Hardware Tasks Function1 Function2 FunctionN

Simulation (by ModelSim)

C compiler for LEON3 CPU SW tasks + HW/SW communication interface Refine C-model to RTL model

Executable files SOFTWARE REFINEMENT

Testbench

EVALUATING ^No

Specification of H.264/

AVC Encoder

Benchmark video sequences

Fig. 4. Design and verification flow.

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The C-Model then is analyzed for identifying the most time-consumption parts by a profiler (e.g. GNU profiler (gprof)). The code-level refinement can be required to modularize the C-Model. Based on the results from previous phases, HW/SW (Hardware/Software) partition phase will partition the overall computation of the algorithm into HW tasks and SW tasks. Each HW task, which is equivalent to a function in C-Model, will be extracted and refined to RTL model. The individual blocks can then be verified in isolation with a suitable test-bench. After RTL model of the module has been verified by the simulation, it can be evaluated further through RTL/C co-emulation environment on the SoC testbed as shown in Fig. 5b. For that purpose, some refinement to C- model is also implemented, such as replacing the module, which needs to be verified at RTL level, with the communication interface that drives the corresponding IP core.

The HW and SW tasks may communicate data with each other through the off-chip SDRAM. Finally, the software tasks and communication tasks will be compiled onto the LEON3 processor by Gaisler’s compiler [10].

Fig. 5. Method for validating the RTL design on the SoC testbed.

V. APPLICATION TO THE H.264/AVCVIDEO ENCODER The H.264/AVC encoder is evaluated with CIF video sequences by both C/RTL simulation and emulation. Firstly, the encoder is divided into several functional modules, which relate to each other by a Control and Data Flow Graph (CDFG). Next, a C software model (C-Model as shown in Fig.

5a) of the encoder is built for untimed functional verification.

The C-Model first run on only LEON3 processor of the SoC testbed for generating the result files that is called Soft_results as shown in Fig. 5a.

Once the design has been refined to the RTL model, and evaluated in terms of function and performance by RTL level simulation, it can be evaluated further through emulation

environment on the SoC testbed. A RTL/C co-emulation model as shown in Fig. 5b is used for verifying the functionality and performance of the implementation of modules or the complete encoder. To verify one certain module (e.g., IME) at RTL-level, this functional module is refined independently to RTL model. At each time, only one function will be verified at the RTL level, the other functions are executed by the C-model running on the LEON3 core. The output result file from co-emulator (called Hard-result as shown in Fig. 5b) is compared with the result from the C- model to validate: if matching, it may continue to simulate and verify the implementation at the RTL-level for the other modules.

After all of functional modules are already validated, they are integrated together into a complete encoder, and continue to be verified on the emulator.

The process of emulating the encoder on the emulation board is described briefly as follows (Fig. 6). Firstly, Linux OS and C-model encoder is compiled and loaded into the Flash memory of the SoC testbed. Next, the benchmark video files are copied into an SDcard, which inserted in the SDcard slot afterwards. These source video files are in ‘raw’ YCbCr format at CIF resolution. After resetting the system, C-model encoder running on LEON3 core analyses the encoding parameters, gets the video frame one-by-one from FLASH memory and writes to SDRAM memory, and starts the encoding process. When software program executes to the location at where the module has been replaced by the communication interface, it transfers all of the necessary control parameters to DMA in wrapper and passes bus control to wrapper (i.e., phase (1) in Fig. 6). DMA will read data from SDRAM and trigger IP core operation (i.e. phase (2) in Fig.

6). DMA is also in charge of writing the result back to SDRAM. When the hardware IP core has done its task, it generates an interrupt signal to notice LEON3, and returns bus control to the CPU (i.e., phase (3) in Fig. 6).

The encoder creates a reconstructed video file, which is identical to decoded video file by a decoder. Therefore, it is able to display the reconstructed frames on a LCD monitor via SVGA controller for evaluating the visual quality of the decoded video file.

Fig. 6. The process of validating one IP core on the emulation board.

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Synthesis results of the SoC testbed are reported by Altera Quartus II as shown in Fig. 7.

Fig. 7. Compilation report by Altera Quartus II.

Fig. 8 shows the demonstrating result of the testbed on the Altera DE2 board, where a CIF@25fps video sequence is encoded by the H.264/AVC video encoder and the reconstructed video sequence is displayed on the LCD screen.

Fig. 8. Testbed implementation on Altera DE2 development board.

VI. CONCLUSIONS

A SoC testbed and platform-based verification method for validating the hardware design of H.264/AVC video encoder

has been presented in the paper. Hardware modules are connected to the system designed around LEON3 processor as custom hardware blocks for HW/SW co-emulation. The interface between the hardware module and SoC is done through the wrapper, so it is quite simple for application, and saves developing time. The experimental results prove that the SoC testbed is valuable to ASIC research and design.

ACKNOWLEDGEMENT

This work has been done in the framework of research project No. QGDA.10.02 (VENGME), funded by Vietnam National University, Hanoi. The project aims at developing a hardware for video encoding system based on the H.264/AVC standard, targeted to mobile applications. We would like to express special thanks to Synopsys for providing EDA tools, CMP and AMS for providing CMOS 0.18µm technology libraries.

REFERENCES

[1] P. Rashinkar. System-On-a-Chip Verification Methodology and Techniques, USA Kluwer Academic, Publishers, 2001.

[2] T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra. Overview of the H.264/AVC Video Coding Standard. IEEE Trans. on Circuits and Systems for Video Technology, Vol.13, No. 7, pp. 560-576, 2003.

[3] I. E. G. Richardson. H.264 and MPEG-4 Video Compression. John Willey & Sons, New York, NY, USA, 2003.

[4] Xuan-Tu Tran, Van-Huan Tran. An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs. REV Journal on Electronics and Communications JEC, Vol. 1, No. 2, pp. 122-129, 2011.

[5] Duy-Hieu Bui, Van-Huan Tran, Van-Mien Nguyen, Duc-Hoang Ngo, Xuan-Tu Tran. A Hardware Architecture for Intra Prediction in H.264/AVC Encoder. In Proceedings of the 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), pp. 95-100, Danang, 2012.

[6] Nam-Khanh Dang, Xuan-Tu Tran. A VLSI Implementation for Inter- Prediction Module in H.264/AVC Encoders. In Proceedings of the 2013 IEICE International Conference on Integrated Circuits, Devices, and Verification (ICDV 2013), Ho Chi Minh city, Vietnam, November 2013.

[7] Ngoc-Mai Nguyen, Xuan-Tu Tran, Pascal Vivet, Suzanne Lesecq. An Efficient Context Adaptive Variable Length Coding Architecture for H.264/AVC Video Encoders. In Proceedings of the 2012 International Conference on Advanced Technologies for Communications (ATC 2012), pp. 158-164, Hanoi, October 2012.

[8] Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Pascal Vivet, Duy- Hieu Bui, Xuan-Tu Tran. Hardware Implementation for Entropy Coding and Byte Stream Packing Engine in H.264/AVC. In Proceedings of the 2013 International Conference on Advanced Technologies for Communications (ATC 2013), pp. 360-365, October 2013.

[9] Gaisler Research. GRLIB IP Core User’s Manual. Version 1.3.0-b4133, Aug. 2013.

[10] Gaisler Research. Bare-C Cross-Compiler System for LEON3 User’s Manual.

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