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CMOS Analog IC Design: Problems and Solutions

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Nguyễn Gia Hào

Academic year: 2023

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MASTER IN MANAGEMENT

The MOS Transistor

F-16: The channel length modulation in a MOS transistor causes the transistor to have a drain current depending on the drain-source voltage. Download free ebooks at bookboon.com Click on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to to read moreClick on the ad to read more on the ad to read moreClick on the ad to read more.

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Basic Gain Stages

E-2: The output resistance of the common-drain stage, where the gain transistor has source and ground connected, is of the order of 1/gm. F-11: The output resistance of a common-source stage biased by an active load is of the order of rds. J-6: The output resistance for a telescoping cascode preset by an ideal current source is of the order of gmr2ds.

D-2: For an ideal differential stage, the output voltage depends only on the differential input voltage. Download free ebooks at bookboon.com Click on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read more Click on the ad to read more Get help now. Download free ebooks at bookboon.com Click on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on ad to read moreClick on the ad to read moreClick on the ad to read more.

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RUN FASTER

Use LTspice to find the output voltage range for RL=5 kΩ, assuming that the voltage across the current source IB must be at least 0.3 V. To find the small-signal gain and output resistance, we draw the small-signal diagram shown below corresponding to Problem 4.6. The small-signal open-circuit voltage gainAvoc is found as vo/vinwithRL=∞, i.e. RLeave from the small-signal diagram.

From the graph, we find the minimum value of the output voltage to be vOmin=−0.192 V, and from the requirement that the voltage at the current source IB must be at least 0.3 V, we find the maximum output voltage to be vOmax= 0.6 V. For the telescoping cascode shown above, use LTspice to find the input bias value VIN required to give an output bias voltage of 0.9 V. Find the small-signal resistance to ground from the node X between the source of M2 and the drain of M1 and find the small-signal voltage gain from the input to node X.

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Multistage Amplifiers

G-18: The dominant pole in a two-phase opamp usually comes from the input to the second phase. For the two-phase opamp shown below, assume that all transistors are in the active region and have a channel length modulation parameter λ=0.1 V−1 and an effective gate voltage|Veff|=0.3 V. Download free ebooks at bookboon.com Click on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read more to readClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read more on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read moreClick on the ad to read more.

The small-signal low-frequency differential gain of the op amp shown above is approximately A: 61 dB. Assuming all transistor capacitances are much less than 1 pF, the frequency of the dominant pole in the opamp above is approx. Assuming all zeros and non-dominant poles have frequencies above 1 GHz, the unity gain frequency of the op amp shown above is approx.

For the folded cascode opamp shown above, assume that all transistors have a channel length L=1 µm and a channel width W =20 µm. Calculate the low-frequency small-signal differential gain and the -3 dB bandwidth for a load capacitance of CL=1.5 pF, which is much larger than the parasitic transistor capacitances. The low-frequency small-signal gain Adis found fromAd=gm1rout=gm1/goutwhereroutis found from Eq.

Hình ảnh

Figure 4.72: LTspice schematic for simulating the frequency response of a common-source stage with an active load.
Figure 4.73: Results from the error log file from a ‘.op’ simulation of the gain stage shown in Fig
Figure 4.81: LTspice schematic for simulating the frequency response of cascode stages with different bias current sources.

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