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Nguyễn Gia Hào

Academic year: 2023

Chia sẻ "Cryptography"


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Văn bản

The covert channel is designed to transfer data indirectly between the client and the server; it was created by Lampson [3]. On the other hand, the bit distribution of the normal channel should be the same distribution of the covert channel [5]. The channel between the client and the server is considered a covert channel that depends on authentication and encryption.

The attacker hardly breaks the secret channel and it is considered more secure if it is undetectable [3, 4]. The secret storage channel uses a data variable to enable the sender and receiver to communicate. I previously discussed that the characteristics of the covert channel are similar to any communication channel.

The secret channel can be noiseless if the data sent by the sender and received data by the receiver are the same with probability 1; otherwise the channel is noisy. 0' or '1'. Nevertheless, if the receiver correctly decodes each bit sent by the transmitter, the hidden channel is considered noiseless. The program stream's hidden channel relies on the program execution stream to convey information.

15–17], try to use covert channel as good channel and it can be used to send legal information between client and server.

Covert channel with authentication leads to secure communication The proposed technique is responsible for creating secure communication chan-

Performance discussion

Conclusion and future work

This chapter is distributed under the terms of the Creative Commons Attribution license (http://creativecommons.org/licenses/ . by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Encryption is used to achieve confidentiality to protect data from theft by a third party (eg, an attacker). In this chapter, we used encryption, authentication, and secret channel to produce a secure communication between acceptable parties.

Secure communication channel between client and server that enables them to transfer data securely and agree keys used for future communication. I would like to thank my friends who stood by me and helped me with my work. This chapter is dedicated to my parents, without whom, by the blessings of Allah, all this work would not be possible.

They have believed in me and any decision I made and are proud of me for any accomplishment I have. In: PST’08: Proceedings of the Sixth Annual Conference on Privacy, Security and Trust; Washington, DC, USA; 2008. In: CCS’06: Proceedings of the 13th ACM Conference on Computer and Communications Security; Virginia, USA; 2006.

In: 28th Annual IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC) 2017; Montreal, QC; 2017. Digital information is very easy to process these days, but it allows unauthorized users to access this information. To protect this information from unauthorized access, cryptography is one of the most powerful and widely used techniques.

There are various cryptographic algorithms out of which the Advanced Encryption Standard (AES) is one of the most widely used symmetric key cryptographic algorithms. The main objective of this chapter is to implement the fast, secure and area-efficient AES algorithm on a reconfigurable platform. In this chapter, the AES algorithm is designed using the Xilinx system generator, implemented on the Nexys-4 DDR FPGA development board, and simulated using MATLAB Simulink.


  • Byte substitution
  • Shift row
  • Mix column
  • Add round key

NIST has begun a development process of FIPS for the AES algorithm, stating that it is the replacement of the DES (Data Encryption Standard) algorithm. The AES algorithm was selected for implementation because it is secure and its components and design principles are fully specified. Due to the use of the Rijndael algorithm, different block and key sizes can be selected, which was not possible in the DES algorithm.

According to the AES standard, this algorithm can only accept 128 block bits and the key size can be selected from bits. Each round includes processes such as byte replacement, shifting rows, mixing columns, and adding round key. High-speed area-efficient implementation of AES algorithm on DOI reconfigurable platform: http://dx.doi.org/10.5772/intechopen.82434.

Each row of the matrix generated by the byte substitution is cyclically shifted to the left. The first row is kept as is, the second row is shifted one byte to the left, the third row is shifted two bytes to the left, and the fourth row is shifted three bytes to the left. In adding a round key phase, 128 bits of the state are exported bitwise with 128 bits of the round key.

If this result belongs to the last round, then the output is ciphertext, otherwise the resulting 128 bits are treated as 16 bytes, and another round starts with a new byte replacement process. This is a column-by-column operation between the four bytes of the state column and a round key word. The remaining nine rounds in decryption consist of processes such as round key addition, reverse shift rows, reverse byte replacement, and reverse shuffle columns.

Add round key: Add round key has its own inverse function since XOR has its own inverse function and the round keys must be selected in reverse order. The first row is left as is, the second row is shifted one position to the right by one byte, the third row is shifted one position to the right by two bytes, and the fourth row is shifted one position to the right by three bytes. Inverse mix column: Transformation in inverse mix column is done using polynomials of degree less than 4 over Galois field (GF) 28 where coefficients are the elements from the state column.

Figure 2 shows s-box of AES algorithm. This s-box consists of all possible combina- combina-tions of 8-bit sequence
Figure 2 shows s-box of AES algorithm. This s-box consists of all possible combina- combina-tions of 8-bit sequence

Literature survey

Implementation of AES algorithm

AES encryption

Each round contains processes such as byte substitution, shift rows, shuffle columns and add round key. Since keys are generated using MATLAB code, only remaining system generator-based models such as byte-substitution, shift-rows, and mix-columns are discussed in this section. Further, each group consists of four multiplication blocks such as mul_blk, mul_blk1, mul_blk2 and mul_blk3.

AES decryption

Each round contains processes such as reverse byte replacement, reverse shift rows, reverse shuffle columns, and round key addition. The inverse round function consists of the inverse box s, the inverse shift row, and the inverse mix column as shown in Figure 18. Each group consists of multiply blocks such as mul_blk, mul_blk1, mul_blk2, and mul_blk3.

Each multiplication block consists of three multipliers mul_2, mul_4, and mul_8 and EX-OR operations.

Tools utilized .1 Software utilized

MATLAB is used to generate the keys and also to get the results in the form of images, whereas Xilinx ISE Design Suite is used to get the synthesis result, the RTL schematic and the walkthrough of this implementation.

Experimental results 1 RTL schematic

Synthesis result

Simulation result

Performance analysis

In the proposed design, an optimized and synthesizable very high-speed integrated circuit (VHSIC) hardware description language (VHDL) code is developed for implementing image as well as 128-bit data encryption to utilize less area and increase the speed. From the synthesis results of the proposed design, it is clear that this system uses only 121 slice registers, and its maximum operating frequency is 1102.536 MHz. Performance analysis is a must to compare the performance of the proposed implementation with existing methods.

So far, various researchers have worked on FPGA-based implementations of the AES algorithm; some of them have optimized speed and.


In this chapter, a fast, area efficient and secure implementation of the AES algorithm on FPGA is presented. In this design, thanks to a better Xilinx system generator-based design, the system is optimized and uses only 121 slice registers at a maximum operating frequency of 1102.536 MHz. FPGA based implementation of AES encryption and decryption with low power multiplexer LUT based S-box.

Comparative analysis of different AES implementation techniques for efficient resource utilization and better performance of an FPGA.

Hình ảnh

Figure 2 shows s-box of AES algorithm. This s-box consists of all possible combina- combina-tions of 8-bit sequence
Figure 3 shows byte substitution stage in AES algorithm.
Figure 3 shows byte substitution stage in AES algorithm.
Figure 2 shows s-box of AES algorithm. This s-box consists of all possible combina- combina-tions of 8-bit sequence

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