• Không có kết quả nào được tìm thấy

High Definition (HD) Video Reference Design (V1) - Intel

Nguyễn Gia Hào

Academic year: 2023

Chia sẻ "High Definition (HD) Video Reference Design (V1) - Intel"


Loading.... (view fulltext now)

Văn bản

Processing Suite User Guide, SDI MegaCore Feature User Guide, DDR and DDR2 SDRAM High-Performance Controller User Guide, and the Nios II Processor manuals on the Altera website. Operating Systems and Software Tool Versions Supported by V-Series Reference Designs Operating System Altera Software Tools Altera Development Kit V1 Windows XP or Linux v8.1 Stratix II GX (2SGX 90) Audio Video Note for Table 2:. 1) The Altera software tools include the Quartus II software, SOPC Builder, Nios II EDS, and the MegaCore IP Library (including the Video and Image Processing Suite). Clocked Video Input The MegaCore function converts from a theoretically clocked video format (such as BT656 or DVI) to the flow-controlled Avalon-ST Video protocol.

The Clocked Video Input MegaCore function removes the horizontal and vertical blanking of input clock video, leaving active picture data. However, in the V1 model, the MegaCore clocked video input function is configured to accept SD-SDI SMPTE 259M (sequential 10-bit data - the least significant 10 bits of the 20-bit wide data received by the SDI function MegaCore) and output to Avalon-ST Video (two 10-bit color planes in parallel). This allows the Clocked Video Input MegaCore feature to support SD-SDI, HD-SDI and 3G-SDI data input at runtime.

The Clocked Video Input MegaCore feature also provides clock-crossing capabilities, allowing video formats running at different frequencies to enter the system. The Clocked Video Input MegaCore function produces data in Y'CbCr 4:2:2 format, 10 bits per color plane, 2 colors parallel for SD-SDI, HD-SDI and 3G-SDI data. The progressive video stream is then scaled by the polyphase algorithm of the parameterizable Scaler MegaCore function (using 12 horizontal and 12 vertical taps).

The Scaler MegaCore feature is configured with an Avalon-MM slave control interface to allow runtime specification of the scaler's output resolution.

Figure 1 shows the directory structure for the reference design files when they have  been extracted from the .zip file.
Figure 1 shows the directory structure for the reference design files when they have been extracted from the .zip file.

Lower Quality Format Conversion)

When the input video is in interlaced format, the motion adaptation algorithm produces a video stream in progressive format. Note that data in this mode is also stored in external memory and supports frame rate conversion. Additionally, when the scaler ratio is changed, software running on the Nios II processor calculates and reloads the appropriate coefficients for improved image quality.

Before mixing the video stream with a background test pattern and another video stream, the video data is buffered in external memory using the Frame Buffer MegaCore function. Buffering is required to smooth out the burstiness of the data flow, due to scaling and synchronization of the two streams input to the mixer.

Mixing the Video Streams

Video Output

The Clocked Video Output MegaCore feature also allows for clock-crossing to provide greater design flexibility by allowing the video processing system clock to be decoupled from the video output pixel clock. The video frame is described using the state registers accessed using the Avalon-MM control port on the Clocked Video Output MegaCore function. If you disable Use Control Port in the MegaWizard interface for the Clocked Video Output MegaCore feature, then the output video format is always the format specified in the MegaWizard interface.

The Clocked Video Output MegaCore feature can be configured to support between 1 to 14 different modes, and each mode has a bank of registers describing the output frame. When the Clocked Video Output MegaCore function receives a new control packet on the Avalon-ST Video input, it searches the state registers for a state that is valid and has a field width and height that match the width and height of the control packet. Once found, the Clocked Video Output MegaCore function restarts the video output with these format settings.

If a matching mode is not found, the video output format remains unchanged and restart does not occur. In addition, the Clocked Video Output MegaCore feature provides a queue where pixels can wait when the DVI output is empty and no pixel data is needed. If this FIFO ever becomes full, then the flow-controlled interface indicates that the clocked video output is not ready for data and the earlier parts of the pipe are blocked.

IP Configurations

SDI MegaCore Function

Clocked Video Input MegaCore Function

Both the VidModeMatch register and the vid_mode_match signal indicate the currently selected mode. Less significant 10 bits of 20-bit wide input data (two 10-bit color planes in sequence, Y' with alternating Cb and Cr) and syncs embedded in the video stream to support SD-SDI. This is enabled by enabling Allow color schemes in sequence input in the parameter settings GUI.

The MegaCore function re-sequences the color planes to output the data as two 10-bit color planes in parallel. Status information, such as image resolution, video persistence, and FIFO fill level, is exposed through register mapping to software control code.

Clipper MegaCore Function

Chroma Resampler MegaCore Function

Color Space Converter MegaCore Function

Deinterlacer MegaCore Function

Scaler MegaCore Function

Frame Buffer MegaCore Functions

DDR2 SDRAM High Performance Controller MegaCore Function

Test Pattern Generator MegaCore Function

Alpha Blending Mixer MegaCore Function


Clocked Video Output MegaCore Function

DVI TX Controller

System Peripherals

Clock Domains

Run Time Resolution Changes

Input Resolution

Viewing Mode

Scaled Up To Output Resolution

Scaled Up To Output Resolution

Board LEDs Status Information

Quad Seven-Segment Display Status Information

For example, the seven-segment display in Figure 10 displays S, 1, 0, H which means high-definition video on stream 1, at 74.175 MHz, with DVI output 59.94 frames per second (Fps) and video in standard definition on broadcast 2.

External Memory Bandwidth Calculations

Reviewing the V1 Reference Design

Top Level

SOPC Builder System

All components of the SOPC Builder system are connected by either Avalon-MM or Avalon-ST interfaces. The Clocked Video Input and Clocked Video Output MegaCore functions form the boundary of the video processing data path, exporting signals for connection to top-level video interfaces (SDI and DVI). To review the configuration of the IP components in SOPC Builder, select the IP module name (for example, my_alt_vip_scl_1) and click Edit.

Close SOPC Builder and click Start Compilation on the Processing menu to compile the Quartus II project.

Figure 11. Complete SOPC Builder System for the V1 Reference Design
Figure 11. Complete SOPC Builder System for the V1 Reference Design


Building the Software in the Nios II IDE

To configure the System Library project, right-click the s2gxav_controller project and click System Library Properties. Verify that Program Never Exits, Clean Exit (flush buffers), Support C++ and Reduced Device Drivers are enabled. To program the Nios II application executable to SRAM from the Nios II IDE, right-click the s2gxav_controller project, point to Run As, and click Nios II Hardware.

1 Altera recommends viewing the .hpp files in the application project to quickly understand the control capabilities of the Nios II software environment.

Figure 13. Nios II IDE New Project Dialog Box
Figure 13. Nios II IDE New Project Dialog Box

Setting Up the Hardware and Configuring the FPGA

You can configure the Stratix II GX90 device by downloading the SRAM object file image (.sof) to the development board. Turn on Program/Configure on the same line as s2gxav.sof in the programming window. 1 No video is displayed on the screen until the executable software has been downloaded to the SRAM.

Downloading the Nios II Software


Error When Re-Compiling the Design

Output Video Does Not Appear on Display

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device names and all other words and logos identified as trademarks and/or service marks are, unless otherwise noted, the trademarks and service marks of Altera Corporation in the U.S. Altera assumes no responsibility or liability arising from the application or use of any information, product or service.

Delay Between a Change of Input and Output

Limited Maximum Resolution of video Stream 2 When Video Stream 1 is 3G-SDI

Revision History

Hình ảnh

Table 1 lists the key features of the V1 reference design.
Figure 1 shows the directory structure for the reference design files when they have  been extracted from the .zip file.
Figure 1. Reference Design Directory Structure
Figure 2. SOPC Builder Design Flow

Tài liệu tham khảo

Tài liệu liên quan

Hiệu quả kỹ thuật, hiệu quả phân phối nguồn lực và hiệu quả sử dụng chi phí Kết quả ước lượng hiệu quả kỹ thuật, hiệu quả phân phối nguồn lực, hiệu quả sử dụng chi phí