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Memory Architectures

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Nguyễn Gia Hào

Academic year: 2023

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Third, the address space of a processor architecture is partitioned to provide access to the different types of memory, to support common programming models, and to designate addresses for interaction with devices other than memory, such as I/O devices.

Memory Technologies

RAM

To achieve reasonable performance at a reasonable price, faster memories must be mixed with slower memories. The time it takes to access one memory address may depend on which memory address was last accessed. A manufacturer of a DRAM memory chip will specify that each memory location needs to be updated, e.g. every 64 ms, and that a number of locations (a "row") are updated together.

The mere act of reading the memory will refresh the locations being read (and locations on the same row), but since applications may not access all rows within the specified time interval, DRAM must be used with a controller that ensures that all locations are refreshed frequently enough to retain the data. The memory controller will stall the access if the memory is busy with a refresh when the access is initiated.

Non-Volatile Memory

Memory Hierarchy

Memory Maps

The total size of the address space is limited by the address width of the processor. This contrasts with the classic von Neumann architecture, which stores program and data in the same memory. It also includes a number of on-chip peripherals, which are devices accessed by the processor using some of the memory addresses in the range from 0x40000000 to 0x5FFFFFFF (range C in the figure).

Some registers can be read to obtain input data that is acquired by a peripheral device. A few addresses in the private peripheral bus area are used to access the interrupt controller. As shown in Figure 9.1, these will be mapped to memory addresses in the range 0xA0000000 to 0xDFFFFFFF (area E).

ARM introduced a clever way to take advantage of these unused addresses called bit banding, where some unused addresses can be used to access individual bits instead of entire bytes or words in memory and peripherals. Rear Admiral Grace Murray Hopper of the United States Navy and funding from IBM were instrumental in making the machine a reality.

Figure 9.1: Memory map of an ARM Cortex TM - M3 architecture.
Figure 9.1: Memory map of an ARM Cortex TM - M3 architecture.

Register Files

Scratchpads and Caches

The valid bit indicates whether the cache line stores meaningful information, while the tag (comprisingt=m−s−bbits) uniquely identifies the block stored in the cache line. Line Matching: The next step is to check if a copy of w is present in the unique cache line for this set. Once this block is fetched, it will replace the block currently occupying the cache line.

Word selection: Once the cache line is found, the word selection is performed as with a direct mapped cache. In case of a miss, replacing the cache line can be more complicated than with a direct map cache. For the latter, there is no choice in replacement, as the new block will displace the current block in the cache line.

However, in the case of set-associative cache, we have an option to select the cache line from which to remove a block. A common policy is least recently used (LRU), which deletes the cache rule whose most recent access occurred furthest in the past.

Figure 9.2: Cache Organization and Address Format. A cache can be viewed as an array of sets, where each set comprises of one or more cache lines
Figure 9.2: Cache Organization and Address Format. A cache can be viewed as an array of sets, where each set comprises of one or more cache lines

Memory Models

  • Memory Addresses
  • Stacks
  • Memory Protection Units
  • Dynamic Memory Allocation
  • Memory Model of C

A stack pointer (usually a register) contains the memory address of the top of the stack. When an item is pushed onto the stack, the stack pointer is incremented and the item is stored in the new location pointed to by the stack pointer. When an item is taken off the stack, the memory location pointed to by the stack pointer is (usually) copied elsewhere (for example, to a register) and the stack pointer is decremented.

The data for a procedure that is pushed onto the stack is known as that procedure's stack frame. It can be catastrophic for firmware if the stack pointer grows beyond the memory allocated to the stack. The contents of this memory location will be overwritten the next time elements are pushed onto the stack.

When the procedure is called on line 11, the stack location will receive the copy of the value of the variable specified on line 8. This is an example of passing by value, where the value of a parameter is copied onto the stack for use by the called procedure.

Summary

Assume that the stack grows from the top (area D) and that the program and static variables are stored at the bottom (area C) of the data and program memory area. Example 10.3: The GPIO pins of the microcontroller shown in Figure 10.1, when configured as inputs, trigger the Schmitt. Example 10.5: The GPIO pins of the microcontroller shown in Figure 10.1, when configured as outputs, can be specified to be open drain circuits.

Suppose the processor's frequency is operating at 18 MHz (relatively slow for a microcontroller). An interrupt service routine can be called between any two instructions of the main program (or between any two lower-priority ISR instructions). The states of the FSMs correspond to positions in the run labeled AthroughE, as shown in the program list.

A C program specifies a series of steps, where each step changes the state of the memory in the machine. In C, the state of the memory in the machine is represented by the values ​​of variables. Example 11.2: In the program in Figure 11.2, the state of the memory of the machine includes the value of variablex (which is a global variable) and a list of elements to which the variable header (another global variable) refers.

The states of the state machine represent positions in the program and the transitions represent the execution of the program. When this transition is taken, newx (on the stack) is assigned the value of the argument. The fourth argument made by topthread is the address of the argument to pass to the start routine.

These constraints tie the execution of a task to real time, which is the physical time in the computer environment that executes the task. For example, assigning a task can be done once for a task, at runtime just before the first execution of the task. It can then adjust the stack pointer to refer to the state of the task about to start or resume.

We can show that the new schedule has a maximum tardiness that is not greater than that of the original schedule. The maximum lateness of the second schedule is given by L0max= max(fi0−di, fj0 −dj). Much of the foundation for work in this area can be found in Harter (1987) and Joseph and Pandya (1986).

You can assume that the comments fully reveal the resource consumption of the procedures.

Figure 10.1: Stellaris  R LM3S8962 evaluation board (Luminary Micro , R 2008a).
Figure 10.1: Stellaris R LM3S8962 evaluation board (Luminary Micro , R 2008a).

Hình ảnh

Figure 9.1: Memory map of an ARM Cortex TM - M3 architecture.
Figure 9.2: Cache Organization and Address Format. A cache can be viewed as an array of sets, where each set comprises of one or more cache lines
Figure 10.1: Stellaris  R LM3S8962 evaluation board (Luminary Micro , R 2008a).
Figure 10.3: A number of open collector circuits wired together.
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