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of Embedded and Cyber-Physical

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Nguyễn Gia Hào

Academic year: 2023

Chia sẻ "of Embedded and Cyber-Physical "

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Peter Marwedel has made many invaluable contributions to research in Electronic Design Automation and in particular Embedded System Design. Already in his early years he set a milestone in the field of high-level synthesis and hardware description languages.

Contributors

Daniel Kästner AbsInt Angewandte Informatik GmbH, Saarbrücken, Tyskland Arno Luppold Institute of Embedded Systems, Hamburg University of Technology (TUHH), Hamborg, Tyskland. Reinhard Wilhelm University of Saarbrücken, Saarbrücken, Tyskland Saehanseul Yi University of California, Irvine, CA, USA.

Peter Marwedel and the Department of Computer Science of the TU Dortmund

  • Introduction
  • Teaching
  • Academic Self-Government
  • Basic Research and SFB 876
  • Technology Transfer and ICD
  • Conclusion

He was the dean of studies of the department and a member of the academic senate of TU Dortmund. Professor Marwedel has contributed significantly to the international recognition of the Department of Computer Science through his research in embedded and cyberphysical systems.

Testing Implementation Soundness of a WCET Analysis Tool

Introduction

  • Tool Qualification
  • Predictability
  • WCET Analysis
  • The Central Idea: Proving Safety Properties
  • Terminology

TQL is determined by the potential impact of the tool and the security level of the software design. In the following, we will focus on the tool qualification requirements of the avionics industry, which are the most stringent of the safety critical industries.

Fig. 2.1 The architecture of the aiT tool
Fig. 2.1 The architecture of the aiT tool

Validation of Our WCET Analysis Tool

  • Control-Flow Graph Reconstruction
  • Value Analysis
  • Microarchitectural Analysis: Trace Validation
    • Semi-Automatic Derivation of the Abstract Architecture Model Nowadays, hardware circuits are automatically synthesized from formal hardware
    • Trace Validation

The reconstruction of the control-flow graph (CFG) of a binary executable means to compute a safe approximation of the inter-procedural control flow of the executable [13]. It is an abstract interpretation of program execution on the underlying cache and pipeline architecture.

Fig. 2.2 Evolution of abstract hardware states s ˆ i . Each edge denotes a single cycle transition in the abstract state space
Fig. 2.2 Evolution of abstract hardware states s ˆ i . Each edge denotes a single cycle transition in the abstract state space

Conclusion

For multicore architectures, such as the TriCore TC275, which contains three different cores, several thousand test cases are required to cover all architectural features. The number of test cases sufficient to cover the (timing) relevant hardware behavior cannot therefore be easily quantified in advance.

The images or other third-party materials in this chapter are included in the chapter's Creative Commons license, unless otherwise indicated in a credit line for the material. If material is not included in the chapter's Creative Commons license and your intended use is not permitted by statutory regulations or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.

The Dynamic Random Access Memory Challenge in Embedded Computing

  • Introduction
  • Bandwidth and Latency
  • Power Consumption
  • Temperature vs. Reliability
  • Safety and Security
  • Conclusion

The memory controller has to manage access to the DRAM memory from the computer structure on the one hand and the complex interface protocol of the DRAMs on the other hand. Sub-threshold leakage (2), which is the drain-source leakage of the cell transistor when it is in the OFF state.

Figure 3.1 shows different DRAM-based memory subsystems, and Figs. 3.2 and 3.3 show their properties with respect to interface frequency, maximum theoretical bandwidth, and energy consumption per transferred bit
Figure 3.1 shows different DRAM-based memory subsystems, and Figs. 3.2 and 3.3 show their properties with respect to interface frequency, maximum theoretical bandwidth, and energy consumption per transferred bit

On the Formalism and Properties of

Timing Analyses in Real-Time Embedded Systems

  • Introduction
  • Formal Analysis Based on Schedule Functions
    • Preemptive EDF
    • Preemptive Fixed-Priority Scheduling Algorithms
  • Utilization-Based Analyses for Fixed-Priority Scheduling
  • Probabilistic Schedulability Tests
  • Conclusion

Burns, Response time upper bounds for fixed priority real-time systems, inReal-Time Systems Symposium pp. Lehoczky, Fixed priority scheduling of periodic task sets with arbitrary deadlines, in Proceedings Real-Time Systems Symposium (RTSS)(1990), pp.

ASSISTECH: An Accidental Journey into Assistive Technology

Balakrishnan

  • The Beginning: Mainly a Facilitator (2000–2005)
  • Early Phase: Focus on Embedded Systems (2005–2010) .1 ASSISTECH and COP315
    • SmartCane
    • OnBoard
  • Collaborations and Research: Formation of ASSISTECH (2010–2013)
    • Student Projects to Research
    • NVDA Activities
  • Change of Focus: Technology to Users (2013–2016) .1 Tactile Graphics Project
    • More Research Projects and International Collaboration
  • Consolidation and Growth (2016 - )
    • RAVI
    • MAVI
    • NAVI
    • Outreach Through Conferences
    • Major Recognitions
  • Conclusion

This was the beginning of the relationship that has played a vital role in ASSISTECH's success. A 30-person user group was involved in the early stages of product design and helped define requirements. One of the visually impaired students in the group (Mr. Akashdeep Bansal) has taken it up as a subject for his PhD research.

He has captured this in the specification and design of an app that can help the visually impaired with outdoor mobility.

Fig. 5.1 SmartCane through various stages of development: Laboratory (2005) to Product (2014)
Fig. 5.1 SmartCane through various stages of development: Laboratory (2005) to Product (2014)

Reflecting on Self-Aware Systems-on-Chip

  • Introduction to Self-Aware Systems-on-Chip
    • Computational Self-Awareness
    • Cyber-Physical Systems-on-Chip
  • Reflective System Models
    • Middleware for Reflective Decision-Making
  • Managing Energy-Efficient Chip Multiprocessors
    • Single Input Single Output Controllers
    • Multiple Input Multiple Output Controllers
    • Adaptive Control Methods
    • Hierarchical Controllers
  • Heterogeneous Mobile Governors: Energy-Efficient Mobile System-on-a-Chip
    • Sensors to Capture Dynamism
    • Toward Self-Aware Governors
  • Adaptive Memory: Managing Runtime Variability
    • Sharing Distributed Memory Space
    • Memory Phase Awareness
    • Quality-Configurable Memory
  • What’s Ahead?
    • Example Use Case: Autonomous Driving
  • Summary

Based on the use of each processing element, games are classified as one of the following classes: (1) No CPU-GPU Dominant; (2) CPU Dominant; (3) GPU Dominant; and (4) CPU-GPU Dominant. By being aware of the periodic patterns, or phasic behavior, of an application's memory usage (memory phases), a system's on-chip memory can be used more efficiently. Herkersdorf, Conquering MPSoC complexity with the principles of a self-ware information processing factory, in Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (ACM, New York, 2016), p.

Venkatasubramanian, On-chip self-awareness using cyberphysical-systems-on-chip (CPSoC), in Proceedings of the 2014 International Conference on Hardware/Sagteware Codesign and System Synthesis, CODES '14 (ACM, New York, 2014), pp.

Fig. 6.1 CPSoC infrastructure: sensors and actuators throughout the system stack, with support for adaptive policies that enforce a given goal (from [3])
Fig. 6.1 CPSoC infrastructure: sensors and actuators throughout the system stack, with support for adaptive policies that enforce a given goal (from [3])

Pushing the Limits of Parallel Discrete Event Simulation for SystemC

  • Introduction
  • RISC Framework
    • RISC Compiler
    • RISC Simulator
    • RISC Analysis and Transformation Tools
  • Experiments
    • Mandelbrot Renderer
  • RISC Open Source Project
    • Open Source Code and Documentation
    • Binary Image for “Plug-and-Play” Evaluation
  • Conclusion

To produce a safe parallel model, the RISC compiler performs three main tasks, namely segment graph construction, conflict analysis, and finally source code instrumentation. However, the RISC compiler must first parse the SystemC input model into an Abstract Syntax Tree (AST). The RISC simulator supports out-of-order discrete event simulation (OoO PDES) [6] for fast SystemC simulation.

Ha, Simulation Environment Configuration for Parallel Simulation of Multicore Embedded Systems, inProceedings of the Design Automation Conference (DAC) (2011), pp.

Fig. 7.1 RISC tool flow for out-of-order parallel simulation of SystemC models [16]
Fig. 7.1 RISC tool flow for out-of-order parallel simulation of SystemC models [16]

Impact of Negative Capacitance Field-Effect Transistor (NCFET)

  • Introduction
    • Negative Capacitance Field-Effect Transistor (NCFET)
  • Modeling NCFET at the System Level
    • Processor-Level Investigation
    • Simulation of NCFET-Based Many-Core
  • Performance, Power, and Cooling Trade-Offs with NCFET-based Many-Cores
    • Impact of NCFET on Performance
    • Impact of NCFET on Cooling Requirements
    • Impact of NCFET on Power Management Techniques
  • NCFET-Aware Voltage Scaling
    • Importance of NCFET-Aware DVS
    • NCFET-Aware DVS Technique
    • Operating Voltage Selection
    • Evaluation
  • Conclusion

This section demonstrates the impact of ferroelectric layer thickness on the power and performance of a multi-core processor. However, due to the lower dynamic power, the leakage power accounts for a larger part of the total power. These studies show that the optimal thickness of the ferroelectric layer depends on the application properties.

NCFET-aware DVS chooses higher voltage most of the time (in this particular example) and reduces power further at the same CPU frequency.

Fig. 8.1 Modeling NCFET at the system level (many-core processors) requires to traverse the whole stack from the physics level, where the effects of the ferroelectric layer are modeled, to the system level, where performance and power of many-core processo
Fig. 8.1 Modeling NCFET at the system level (many-core processors) requires to traverse the whole stack from the physics level, where the effects of the ferroelectric layer are modeled, to the system level, where performance and power of many-core processo

Run-Time Enforcement of

Non-functional Program Properties on MPSoCs

Introduction

Runtime state uncertainty. This source of uncertainty originates either from the environment (called exogenous), e.g., ambient temperature, or from within the computer system itself (called endogenous), e.g., cache states or voltage modifications/ frequency applied by the energy manager. While the vast majority of exogenous sources of uncertainty cannot be avoided or controlled, endogenous sources of uncertainty can be eliminated, e.g., by flushing caches before execution or setting the voltage/frequency of each core to a fixed desired level . In the presence of runtime and input state uncertainties, application-specific runtime techniques can provide a practical approach to constrain non-functional runtime properties within acceptable limits or to prevent requirement violations.

Such techniques dynamically adjust a given set of control knobs, e.g., voltage/frequency settings, in response to observed (or predicted) changes in input and/or environmental conditions to drive non-functional performance properties. within the desired range.

Preliminaries and Definitions .1 System Model

Here, runtime requirement enforcement techniques can apply to control the resources of the platform based on runtime monitoring to stay within the requirement corridors. For such partially satisfactory implementations, runtime techniques can be used to make them consistently satisfactory by regularly monitoring (or predicting) the online input/state scenario and either acting proactively to prevent any violation of a set of given requirements, e.g. the voltage/frequency settings of cores prior to program execution, or in response to an observed violation. The goal of such runtime techniques is therefore to enforce that the desired latency and power corridor are never (or only occasionally) violated.

These application-specific implementation techniques are referred to hereafter as implementation requirement enforcement (RRE).

Run-Time Requirement Enforcement

Three implementations of the program are shown. p1 does not meet the delay requirement for eventual execution. p2 satisfies two requirements for possible changes in input∈I and stateq∈Q. Also depicted is an RRE whose task is to limit the observed predictability interval p within a corridor defined by delay and power requirements. Given the actual (current) input iact ∈I and the state qact ∈Q, the RRE in this case proactively estimates the expected delay Lestand power consumptionPest, based on which it takes actions (output arcs of the RRE) with the aim of avoiding any violation of the requirements.

Examples of RRE actions include adjusting the voltage/frequency of the cores or awake reserved cores that are currently in a sleep state for power reduction, or even changing the mapping of some tasks to other cores [14].

Taxonomy of Run-Time Requirement Enforcers

  • Enforcement Automata (EA)
  • i-lets and e-lets

Here, the execution time of the 9 tasks (actors) of the application is monitored by a local so-called Run-Time Requirement Monitor (RRM) which is instantiated on each of the invaded tiles. Thus, each actor in the chain is provided with the information about the time that has already passed for the processing of the frame by the previous actors on the basis of which it determines the slack available for the rest of the processing. As illustrated, the RRE acts as an interface between the application and the system software of the tile.

While e-lets are always considered the preferred executive entities of the application program, they dominate the i-lets also included in this program.

Fig. 9.4 Centralized RRE
Fig. 9.4 Centralized RRE

Case Study

  • Enforcement Problem Description
  • Power, Latency, and Energy Model
  • Energy-Minimized Timing Enforcement
  • Distributed Enforcement
  • Centralized Enforcement
  • Lower Latency Bound Enforcement and Range Extenders

Figure 9.8 illustrates the distribution (left) and the cumulative distribution (right) of the per-feature latency for the SD actor. The histograms of observable latencies of the SD and SM actors (a) without enforcement (n=4 andm=20) and (b) with enforcement taking into account hard (s=1) latency upper bounds of UBL=80 ms and 15 ms for SD and SM, respectively, are illustrated in Fig.9.11. In this section, we consider the combined enforcement of the SD and SM actors using centralized enforcement.

The histogram of observable collective latency of the SD and SM actors (a) without enforcement (n = 4 and m = 20 for both actors) and (b) with enforcement considering a hard latency upper bound, i.e. for stringency of requirements ofs =1, is illustrated in Fig.9.13.

Table 9.1 Average, standard deviation, and overall contribution to the overall latency of each actor of the object detection application in Fig
Table 9.1 Average, standard deviation, and overall contribution to the overall latency of each actor of the object detection application in Fig

Conclusions

Altmeyer, et al., A generic and compositional framework for multicore response time analysis, in Proceeding of RTNS (ACM, New York, 2015), p. basic systems. Schwarzer, et al., Exploring the symmetry-eliminating design space for mapping hybrid applications to multi-core architectures.

Weichslgartner, et al., Invasive Computing for Mapping Parallel Programs to Multicore Architectures (Springer, Berlin, 2018).

Compilation for Real-Time Systems a Decade After P REDATOR

  • Introduction
  • Challenges and State-of-the-Art in WCET-Aware Compilation During P REDATOR
  • Integration of Task Coordination into WCET-Aware Compilation
  • Analysis and Optimization of Multi-Processor Systems on Chip
  • Multi-Objective Compiler Optimizations Under Real-Time Constraints
  • Conclusions

Section 10.2 puts the state of the art in compiling for real-time systems at the end of PREDATOR into a nutshell. The planning test from Eq. 10.6) must only be modeled in ILP at the discontinuity points of the problem set's density functionsη. The 100% baseline in Fig.10.7 indicates the WCETs and code sizes for the original, unoptimized benchmarks, respectively.

Gresser, An event model for deadline verification of hard real-time systems, in Proceedings of the 5th Euromicro Workshop on Real-Time Systems (ECRTS)(1993).https://doi.org/10.1109/.

Figure 10.1 shows the effect of our ILP-based multi-task SPM allocation on schedulability of task sets featuring 8 tasks
Figure 10.1 shows the effect of our ILP-based multi-task SPM allocation on schedulability of task sets featuring 8 tasks

Index

Multiprocessor Systems, Analysis and Optimization (continued) MPSoC Architectures, 159 MRTC's Selected Benchmark, 162 Multiprocessor Systems on Chip (MPSoC),. Non-Visual Desk Top Access (NVDA), 68 NSF, see National Science Foundation (NSF) NVDA, see Non-Visual Desk Top Access. Recoding Infrastructure for SystemC (RISC) analysis and transformation tools, 101 compiler (see RISC compiler) EDA community, 104 IEEE SystemC language, 97 Mandelbrot renderer, 101–102 OoO PDES, 104.

Hình ảnh

Fig. 2.1 The architecture of the aiT tool
Figure 3.1 shows different DRAM-based memory subsystems, and Figs. 3.2 and 3.3 show their properties with respect to interface frequency, maximum theoretical bandwidth, and energy consumption per transferred bit
Fig. 3.2 Interface frequency and maximum bandwidth of different DRAM types
Fig. 5.1 SmartCane through various stages of development: Laboratory (2005) to Product (2014)
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