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Serial ATA Advanced Host Controller Interface (AHCI) - Intel

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Academic year: 2023

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Outside of Scope

Block Diagram



Theory of Operation

This command list can be used by system software and the HBA even when non-queued commands need to be transferred. It is the system software's responsibility not to mix queued and unqueued commands in the command list.

Interaction with Legacy Software

System software can still put multiple commands on the list, be it DMA, PIO, or ATAPI, and the HBA must go on the list and transfer them. This reuse of the command list is achieved by the HBA moving its command list pointer only when the BSY, DRQ, and ERR bits are cleared by the device.

This section describes how to build the PCI Header and PCI Capabilities for an AHCI HBA. The PCI specifications are the normative specifications for these registers and this section describes additional requirements for an AHCI HBA.

PCI Header

  • Offset 00h: ID - Identifiers
  • Offset 04h: CMD - Command
  • Offset 06h: STS - Device Status
  • Offset 08h: RID - Revision ID
  • Offset 09h: CC - Class Code
  • Offset 0Ch: CLS – Cache Line Size
  • Offset 0Dh: MLT – Master Latency Timer
  • Offset 0Eh: HTYPE – Header Type
  • Offset 0Fh: BIST – Built In Self Test (Optional)
  • Offset 10h – 20h: BARS – Other Base Addresses (Optional)
  • Offset 24h: ABAR – AHCI Base Address
  • Offset 2Ch: SS - Sub System Identifiers
  • Offset 30h: EROM – Expansion ROM (Optional)
  • Offset 34h: CAP – Capabilities Pointer
  • Offset 3Ch: INTR - Interrupt Information
  • Offset 3Eh: MGNT – Minimum Grant (Optional)
  • Offset 3Fh: MLAT – Maximum Latency (Optional)

Bus Master Enable (BME): Controls the ability of the HBA to act as a master for data transfers. This bit should only be read if the bus master IDE is not supported by the HBA.

PCI Power Management Capabilities

Offset PMCAP: PID - PCI Power Management Capability ID

07:00 RW 00h Interrupt Line (ILINE): Software written value to indicate which interrupt line (vector) the interrupt is connected to. Grant (GNT): Specifies the minimum grant time (in ¼ microseconds) the device wishes to grant.

Informational Note: If the HBA is a single-function PCI device, INTR.IPIN must be set to 01h to indicate the INTA# pin.

Offset PMCAP + 4h: PMCS – PCI Power Management Control And Status

Message Signaled Interrupt Capability (Optional)

  • Offset MSICAP: MID – Message Signaled Interrupt Identifiers
  • Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control
  • Offset MSICAP + 4h: MA – Message Signaled Interrupt Message Address
  • Offset MSICAP + (8h or Ch): MD – Message Signaled Interrupt Message Data
  • Offset MSICAP + 8h: MUA – Message Signaled Interrupt Upper Address (Optional)

Its contents are driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI memory write transaction.

Other Capability Pointers

All registers starting under address 100h are global and should apply to the entire HBA. Port control registers are the same for all ports, and there are as many banks of registers as there are ports.

Generic Host Control

  • Offset 00h: CAP – HBA Capabilities
  • Offset 04h: GHC – Global HBA Control
  • Offset 08h: IS – Interrupt Status Register
  • Offset 0Ch: PI – Ports Implemented
  • Offset 10h: VS – AHCI Version

Slumber State Capable (SSC): Indicates whether the HBA can support Slumber state transitions. Partially Capable (PSC): Indicates whether the HBA can support partial state transitions.

Vendor Specific Registers

Port Registers (one set per port)

  • Offset 100h: P0CLB – Port 0 Command List Base Address
  • Offset 104h: P0CLBU – Port 0 Command List Base Address Upper 32-bits
  • Offset 108h: P0FB – Port 0 FIS Base Address
  • Offset 10Ch: P0FBU – Port 0 FIS Base Address Upper 32-bits
  • Offset 110h: P0IS – Port 0 Interrupt Status
  • Offset 114h: P0IE – Port 0 Interrupt Enable
  • Offset 118h: P0CMD – Port 0 Command
  • Offset 120h: P0TFD – Port 0 Task File Data
  • Offset 124h: P0SIG – Port 0 Signature
  • Offset 128h: P0SSTS – Port 0 Serial ATA Status (SCR0: SStatus)
  • Offset 12Ch: P0SCTL – Port 0 Serial ATA Control (SCR2: SControl)
  • Offset 130h: P0SERR – Port 0 Serial ATA Error (SCR1: SError)
  • Offset 134h: P0SACT – Port 0 Serial ATA Active (SCR3: SActive)
  • Offset 138h: P0CI – Port 0 Command Issue
  • Offset 170h to 17Fh: P0VS – Vendor Specific

Device Interrupt Enable (DIE): When set and P0IS.DIS is set, the HBA will generate an interrupt. 04 RW 0 FIS Unknown Interrupt Enable (UFE): When set, GHC.IE is set and P0IS.UFS is set to '1', the HBA will generate an interrupt.

HBA Memory Space Usage

Port Memory Usage

Received FIS Structure

When a DMA setup FIS arrives from the device, the HBA copies it to the DSFIS area of ​​this structure. When a PIO Setup FIS arrives from the device, the HBA copies it to the PSFIS area of ​​this structure. When a D2H Register FIS arrives from the device, the HBA copies it to the RFIS area of ​​this structure.

Command List Structure

Note: The HBA can pre-receive ATAPI command, PRD inputs and data regardless of the state of this bit. The HBA may pre-receive data from the CTBAz[ACMD] pending receipt of the PIO Setup FIS. The HBA uses this field to know the length of the FIS to send to the device.

Figure 8: DW 0 – Description Information
Figure 8: DW 0 – Description Information

Command Table

Upper 32-bit Database Address (DBAU): This is the upper 32-bits of the physical address of the data block. Interrupt on Completion (I): When set, indicates that the hardware must assert an interrupt when the data block for this entry is transferred, indicating that there is no data in the hardware HBA. Data Byte Count (DBC): A '0' based value indicating the length of the data block in bytes.

Figure 13: DW 0 – Data Base Address  Bit  Description
Figure 13: DW 0 – Data Base Address Bit Description


HBA State Machine (Normative)

  • Variables
  • HBA Idle States
  • Aggressive Power Management States
  • Non-Data FIS Receive States
  • Command Transfer States
  • ATAPI Command Transfer States
  • D2H Register FIS Receive States
  • PIO Setup Receive States
  • Data Transmit States
  • Data Receive States
  • DMA Setup Receive States
  • Set Device Bits States
  • Unknown FIS Receive States
  • BIST States
  • Error States

Else (transfer successful, R_OK received) → H:Idle This state is entered to transfer the ATAPI command to the device. This state is entered when the interrupt bit 'I' is set in the received D2H FIS register. This state is entered when the HBA encounters a recoverable error.

HBA Rules (Normative)

PRD Byte Count Updates

This state is entered when a BIST Activate FIS is sent by the HBA to the device or received from the device. When a fatal condition occurs, the HBA requires PxCMD.ST to be cleared to recover. When a non-fatal condition occurs, the HBA must return to H:Idle after handling the error.

PRD Interrupt

The PRD Byte Count field is updated according to the number of words specified in the PRD table, disregarding any additional padding.

System Software Rules (Normative)

Basic Steps when Building a Command

Setting CH(z).P

Processing Completed Commands

Software clears appropriate bits in the PxIS register corresponding to the cause of the interruption. If there were errors noted either in the PxIS registry or PxTFD.STS.ERR, the software performs error recovery actions (see Section 6.2.2).

Transfer Examples (Informative)

  • Macro States
  • DMA Data Transfers
  • PIO Data Transfers
  • HBA Assisted Queued DMA Transfers

If the 'I' bit is not set to '1', the HBA will traverse the Exam:D2HNoIntr state. The HBA will transmit the command to the device traversing the macro states Exam:Fetch and Exam:Send. When it arrives, the HBA will accept the FIS by passing the Exam:AcceptNotData macro state.

Error Types

  • System Memory Errors
  • Interface Errors
  • Port Multiplier Errors
  • Device Errors
  • Command List Overflow
  • Command List Underflow
  • Native Command Queuing Tag Errors
  • PIO Data Transfer Errors

If the PhyRdy signal drops during a command, the HBA may need to be rebooted. Calculated CRC different than received: When this happens, the HBA returns R_ERR and reverts to idle. The HBA will remove the package and will not update any registers or memory structures based on the FIS contents.

Error Recovery

HBA Aborting a Transfer

For PIO writes, the HBA receives the PIO Setup FIS and therefore knows the length and can therefore optionally set PxIS.OFS. The HBA must ensure that the size of the data FIS received during a PIO command matches the size in the Transfer Count field of the previous PIO Setup FIS. If the data FIS size does not match the Transfer Count field in the previous PIO setup, the HBA shall respond with R_ERR to the data FIS, set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and then stop running until the software reboots the port.

Software Error Recovery

To detect this condition, software must check to see if PxIS.PCS is set to '1' on an interrupt. Therefore, when software detects that PxIS.PCS is set, software must first issue a COMRESET to ensure that the device receives a COMRESET. To recover, software must perform error recovery actions for a fatal error condition (including restarting the controller).

Platforms that Support Cold Presence Detect

Device Hot Unplugged

Device Hot Plugged

Platforms that Support Interlock Switches

Native Hot Plug Support

Hot Plug Removal Detection and Power Management Interaction (Informative)

During normal operation, the software should check PxIS.PRCS to determine if a hot plug removal has occurred. To take advantage of power management on a port and avoid spurious interrupts due to PhyRdy transitions, software should disable the hot plug removal interrupt. During normal operation, the software should check that PxSSTS.DET is set to 3h to ensure that a hot plug removal has not occurred.

Interaction of the Command List and Port Change Status


Power State Mappings

Power State Transitions

Interface Power Management

Software must set the PxSCTL.IPM field to disable the interface transition to an unsupported power management state. If CAP.SSC or CAP.PSC is set to '0', the software must disable device-initiated power management by sending the appropriate SET FEATURES command to the device. The Serial ATA 1.0a specification defines proper link layer behavior when host-initiated and device-initiated power state transitions occur simultaneously.

Device D1, D3 States

Therefore, if the HBA and the software request go into different states at the same time, the HBA request takes precedence over the software request.

HBA D3 state


Port Multiplier support for HBAs is optional and its support is specified for system software via CAP.SPM.

Command Based Switching

Non-Queued Operation

To find the best slot to place the next command, the software must use PxCMD.CCS to find the current slot that the HBA is running and place the command in the appropriate slot for the desired fairness algorithm.

Queued Operation

Port Multiplier Enumeration

Software Initialization of HBA

Firmware Specific Initialization

System Software Specific Initialization

System software places a port in the idle state by clearing PxCMD.ST and waiting for PxCMD.CR to return '0' when read. If PxCMD.FRE is set to '1', software must clear it to '0' and wait at least 500 milliseconds for PxCMD.FR to return '0' when read. After setting PxFB and PxFBU to the physical address of the FIS receiving area, system software will set PxCMD.FRE to '1'.

Hardware Prerequisites to Enable/Disable GHC.AE

If PxCMD.CR or PxCMD.FR is not cleared to '0' correctly, then the software can try a port reset or a full HBA reset to recover it. It is good practice for the system software to "zero" the memory allocated and referenced by PxCLB and PxFB. Then the software should clear the GHC.IE bit to '0' to ensure that there are no interrupts occurring in the AHCI controller.

Software Manipulation of Port DMA Engines

Start (PxCMD.ST)

FIS Receive Enable (PxCMD.FRE)


Device Reset

To issue a software reset in AHCI, software builds two H2D Register FISs in the command list. The first Register FIS has the SRST bit set to '1' in the Control Field of the Register FIS, the 'C' bit is set to '0' in the Register FIS, and the command table has the CHz[R] (reset ) and CHz[C] (clear BSY on R_OK) bits set to. The second Register FIS has the SRST bit set to '0' in the Control Field of the Register FIS, the 'C' bit is set to '0' in the Register FIS, and the command table has the CHz[R] (reset ) and CHz[C] (clear BSY on R_OK) bits cleared to '0'.

Port Reset

Older software included a standard mechanism for generating a reset to a Serial ATA device – setting the SRST (software reset) bit in the Device Control register. The CHz[C] (make BSY on R_OK) bit must be set for the first Register FIS to clear the BSY bit and continue to issue the next Register FIS since the device does not respond to the first Register FIS in a software does not send recovery sequence. Refer to the Serial ATA 1.0a specification for more information on the software reset FIS sequence.

HBA Reset

Before issuing a software reset, the software must clear PxCMD.ST, wait until the port is idle (PxCMD.CR = ‘0’), and then reset PxCMD.ST. If PxTFD.STS.BSY or PxTFD.STS.DRQ is still set based on a failed command, a port reset should be attempted. If the HBA supports offset rotation, the PxCMD.SUD bit will be reset to '0'; the software is responsible for properly setting the PxCMD.SUD and PxSCTL.DET fields so that communication can be established on the Serial ATA link.

Interface Speed Support

If the HBA does not support staggered spin-up, the HBA reset will cause a COMRESET to be sent to the port.


Tiered Operation

This bit is only a mask and does not affect the setting of any interrupt status bit in any of the ports. This register allows the software to quickly scan the HBA to see which ports are reporting interrupts. The status bit in PxIS is always set regardless of the setting of the corresponding PxIE bit.

HBA/SW Interaction

This is a bit-mapped register that indicates one bit for each of the 32 ports allowed in AHCI. It is set by the level of the virtual interrupt line which is an array, and is cleared by a "1" write by software. When enabled for multi-message generation, interrupt generation is no longer controlled through the IS register.

Table 2: Port/MSI Message Mapping, Example 1  Port  Interrupt Message
Table 2: Port/MSI Message Mapping, Example 1 Port Interrupt Message

Disabling Device Interrupts (NIEN Bit in Device Control Register)

Interlock Switch Operation

Cold Presence Detect Operation

Staggered Spin-up Operation

  • Interaction of PxSCTL.DET and PxCMD.SUD
  • Spin-Up Procedure (Informative)
  • Preparing for Low Power System State (Informative)
  • When to Enter Listen Mode (Informative)

In systems that support incremental spin-up, there is an interaction between PxSCTL.DET and PxCMD.SUD in controlling the behavior of Phy. For platforms that support incremental rotation, PxCMD.SUD also manipulates the behavior of Phy. In listening mode (PxSCTL.DET = 0h and PxCMD.SUD = 0), the HBA Phy can enter a reduced power consumption state equivalent to the power consumption in the Slumber power management state.

Asynchronous Notification

In this case listening mode should be entered to save power on the port while still allowing a hotplug insertion event to be detected via PxSERR.DIAG.X. Listen mode should also be entered to save power when a drive is present on a port and the system is about to enter a low power state, refer to section 10.9.3. Listen mode should not be used if interlocked switch or cold presence detection is supported on the port.

Activity LED

Once the interface is no longer in the active power state as specified by PxSSTS.IPM, set PxSCTL.DET = 0h and PxCMD.SUD = 0h to enter listening mode. This process ensures that the scaled rotation can be used in the transition of the system to S0. In this case, the Phy for the port should be set to offline mode to save maximum power since any hot plug insertion can be detected using the interleaved switch or with cold presence interrupt detection.


Enclosure Management Services

Hình ảnh

Figure 1: IA Based System Diagram
Figure 2: Embedded System Diagram
Figure 3: Example of HBA Silicon Supporting Both Legacy and AHCI Interfaces
Figure 4: HBA Memory Space Usage

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