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Nguyễn Gia Hào

Academic year: 2023

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In particular, I would like to express my thanks to Mir Muntasir Hossain, Graduate Student at Ahsanullah University of Science and Technology, Dhaka, Bangladesh, for drawing my attention to the modeling of FinFET transistors and for co-authoring Example 7.3 about FinFET models. The program also includes a 'Help' function with detailed descriptions of the commands and options in the program. The keyboard shortcut to 'Help' is 'F1' in the Windows version and '?' in the Mac version.

Help' (type 'F1'), select the 'Contents' tab, click the 'Print' symbol and select 'Print the selected heading and all subtopics' in the dialog box that opens. For transistors, the small signal parameters calculated by a 'DC operating point' simulation ('.op') are listed in the 'Spice Error Log' along with the bias values ​​for voltages and currents. Also for an 'AC analysis' the small signal transistor parameters for the bias point are listed in the 'Spice Error Log'.

Not only in the chart sheet, but also in waveform plots, a right-click opens a menu with several sub-menus. The commands for copying charts and waveform plots to the clipboard can be found in the sub-menu 'View → Insert Bitmap'.

Resistive Circuits

For the voltage source 'VS', the positive direction of current flow is in the positive terminal of the voltage source. The Thévenin voltage has already been found by simulating the circuit in Fig. You may notice that many of the commands described for the waveform plot are also available by using a right-click in the plot.

In the component selection box (Fig. 1.3) you can select either 'g' or 'g2', the only difference being the polarity of the control voltage. Next, let's see what happens if we change the current-controlled power source specification to We simply change the name and value of the controlled current source and run the simulation again.

1.32 (with the signal source resistance labeled 'RS' rectified) and the circuit from Fig. For the circuit shown above, determine the value of the voltagesv1andv2 and the current. The value of one of the resistors and the transconductance value of the voltage-controlled current source are unknown.

The other devices have the values ​​shown in the figure along with the values ​​of two of the currents in the circuit.

Figure 1.2: Some toolbar symbols.
Figure 1.2: Some toolbar symbols.

Circuits with Capacitors and Inductors

The figure also shows a window with coordinates for the cursor position. Be aware that AC analysis is a small signal analysis calculated from the bias point of the circuit. Note that the diode model name has been changed from the default 'D' to 'IdealDiode' by right-clicking on the 'D' in the diode symbol and changing it to.

Analytically, at dc (i.e. ω=0), the gain cannot be found and the input node to the inverting input of the amplifier floating. With an input voltage of vS=0 V, this gives an initial value of the output voltage of vO=−AvF =−5 V. It is clear that the gain of the circuit is about 3 V/V as expected and that the output voltage is offset by -5 V.

To simulate the discharge, simply remove the voltage source vS and set an initial value of 3 V for the capacitor voltage vC, see the figure. Of course, a similar approach can be used to analyze the magnetization and demagnetization of an inductor using the specification of the initial value of the current in the inductor. As an alternative to simply inspecting the charge and discharge using a waveform graph and pointer as shown in Figure 1.

After running the simulation, the output of the '.meas' directive is found in the error log file ('Ctrl-L'). The SPICE '.meas' directive provides a very versatile option for post-processing simulation results. Similarly, the initial value of the current in an inductor can be specified by a '.ic' SPICE directive.

When specifying mathematical expressions in the waveform viewer, 'e' (or 'E') is the base of the natural logarithm. Plot the voltage of the capacitor against time and find the time constants for charging and discharging capacitor C. Also assume that the initial value of the input and output voltage is att=0 0 V and that the input current pulses have a rise and fall time of 1 ns.

What initial value of the input voltage Vin will result in a mean value of 0 V for the output voltage Envo. Find the DC output voltage fort→∞and find the time required for VO to reach 90% of the final value.

Figure 2.2: Specification window for the voltage source v S .
Figure 2.2: Specification window for the voltage source v S .

MOS Transistors

The figure also shows the model statements that define the process parameters for each of the transistors. Parameters of small signal transistors: The characteristics of small signal transistors are very important in the design of analog CMOS circuits. For the Shichman-Hodges model for an NMOS transistor in the active region, see Eq.

Also note that the BSIM3 model does not yield values ​​for small-signal capacitances in the same way as the Shichman-Hodges model. For the two curves corresponding to VDS=2.5 V and 3.0 V, the transistor is in the active region for the simulated range of VGS, and the curves show a parabolic relationship between ID and VGS. For other values ​​of VDS, the transistor is in the triode region for large values ​​of VGS, leading to a linear relationship between ID and VGS.

The indicator opens with a horizontal value in the middle of the graph (ie VGS=1.5V) and is attached to the first trace, ie. trace corresponding to VDS=0 V. Note that for VDS=0 (green traces), the transistor is off and for VDS=0.5 V (blue traces), the transistor is in the triode region for small VSB values. All features simulated in the previous examples were based on a simple Shichman-Hodges model.

This is shown in Figure 3.25, which shows the simulated input and output characteristics for both transistors on the same graph. At a threshold voltage Vt of about 0.5V, this means that the transistor is in the active region for the simulated VG range when VG>Vt. With VGS=VDS the transistor is in the active region and from the small signal diagram the input resistance is found to be (gm+gds)-1.

They are listed in the error log resulting from a '.op' simulation as shown in Fig. A '.op' simulation results in the capacitance values ​​listed in the log file shown in Fig. Find the bias current ID and small signal parameterstgm,gmbandgdsforL=1μm and forL=5μm at the bias point.

Simulate and plot the input characteristics (ID vs. VSG) and output characteristics (ID vs. VSD) using the BSIM model and the Shichman-Hodges model with parameters estimated from the simulation of the small-signal parameters at the bias point. From the gm and gds plots, find the maximum drain current at which the transistor is in the active region for each of the three channel width values.

Figure 3.2: Normal textbook definitions of sign conventions for transistor currents and voltages
Figure 3.2: Normal textbook definitions of sign conventions for transistor currents and voltages

Basic Gain Stages

The transistors are specified to be identical by right-clicking on the transistor symbol and entering the transistor parameters in the specification window as shown in Fig. The topmost transistor (M1) shows only the name ('M1') and the transistor model ('NMOS-SH'), and this is LTspice's default way of showing the transistor. When you "Ctrl-right-click" on the transistor symbol, the "Component Attributes Editor" opens that appears to the left of the symbol.

Here you will see the model name (“NMOS-SH”) listed as “Value” and the transistor specification parameters listed as “Value2”. This specifies that only the name ('M1') and the transistor model ('NMOS-SH') are visible in the schematic. This is achieved by inserting an X in the 'Component Attribute Editor' before the line containing 'Value2' as shown to the left of the transistor.

The bottom transistor (M3) shows only LandW in addition to the name ('M3') and the transistor model ('NMOS-SH'). To the left of the transistor symbol, the 'Component Attribute Editor' is shown to achieve this. The transistor specification in the netlist is the same for the three transistors ('View → SPICE Netlist').

In fact, you can also use the 'Component Attribute Editor' for transistor symbols 'nmos' and. 3.1, 'Ctrl-right click' on the symbol and enter the transistor parameters directly into the 'Component Attribute Editor' as shown in the figure. Clearly, this transistor arrangement is more complex than just a simple default specification.

Iterative design of the transistor channel width: to solve the calculations of Eq. To obtain greater gain, the value of RD can be increased or the transistor width can be increased. This means that when drawing the schematic in LTspice you have to rotate ('Ctrl-R') and mirror ('Ctrl-E') the transistor.

Figure 4.2: LTspice schematic for simulating the common-source stage with the Shichman-Hodges transistor model and with λ = 0.16 V −1 and the corresponding value of input bias voltage, i.e., a dc value of 0.84 V for V IN .
Figure 4.2: LTspice schematic for simulating the common-source stage with the Shichman-Hodges transistor model and with λ = 0.16 V −1 and the corresponding value of input bias voltage, i.e., a dc value of 0.84 V for V IN .

Hình ảnh

Figure 1.12: Command selection menu (a) and dialogue box (b) for entering simulation results on the schematic.
Figure 1.14: Plot of dc sweep simulation for circuit example from Fig. 1.4 using the LTspice default setup of colors.
Figure 1.23: Window for defining search path to symbol folders and library folders.
Figure 1.31: Circuit from Fig. 1.30 redrawn with a current-controlled current source instead of an arbitrary-controlled current source.
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