7 4 0
0 0 0 0 0 0 0 0
INTCON
Range Bit
Default
Access and Field Name (ID): Description
7:0 0h RW
INTCON: Used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates to which input of the system interrupt controller the device's interrupt pin is connected.
Type: CFG
(Size: 8 bits) Offset: [B:0, D:2, F:0] + 3Dh
7 4 0
0 0 0 0 0 0 0 1
INTPIN
Range Bit
Default
Access and Field Name (ID): Description
7:0 1h RO
INTPIN: As a single function device, the Processor Graphics specifies INTA# as its interrupt pin.
01h:INTA#.
4.19 Minimum Grant (MINGNT)—Offset 3Eh
The Processor Graphics has no requirement for the settings of Latency Timers.
Access Method
Default: 0h
4.20 Maximum Latency (MAXLAT)—Offset 3Fh
The Processor Graphics has no requirement for the settings of Latency Timers.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits) Offset: [B:0, D:2, F:0] + 3Eh
7 4 0
0 0 0 0 0 0 0 0
MGV
Range Bit
Default
Access and Field Name (ID): Description 7:0 0h
RO MGV: The Processor Graphics does not burst as a PCI compliant master.
Type: CFG
(Size: 8 bits) Offset: [B:0, D:2, F:0] + 3Fh
7 4 0
0 0 0 0 0 0 0 0
MLV
Range Bit
Default
Access and Field Name (ID): Description
4.21 Capabilities A (CAPID0)—Offset 44h
Control of bits in this register are only required for customer visible SKU differentiation.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits) Offset: [B:0, D:2, F:0] + 44h
31 2
8 2
4 2
0 1
6 1
2 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD ECCDIS RSVD VTDD RSVD DDPCD X2APIC_EN PDCD RSVD
Range Bit
Default
Access and Field Name (ID): Description 31:26 0h
RO Reserved (RSVD): Reserved.
25 0h RO_V
ECCDIS:
0b ECC capable 1b Not ECC capable 24 0h
RO
Reserved (RSVD): Reserved.
23 0h RO_V
VTDD:
0: Enable VTd 1: Disable VTd 22:15 0h
RO Reserved (RSVD): Reserved.
14 0h RO_V
DDPCD: Allows Dual Channel operation but only supports 1 DIMM per channel.
0: 2 DIMMs per channel enabled
1: 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank population field for each channel to zero. (MCHBAR offset 260h, bits 22-23 for channel 0 and MCHBAR offset 660h, bits 22-23 for channel 1)
13 0h RO_V
X2APIC_EN: Extended Interrupt Mode.
0b: Hardware does not support Extended APIC mode.
1b: Hardware supports Extended APIC mode.
12 0h RO_V
PDCD:
0: Capable of Dual Channels
1: Not Capable of Dual Channel - only single channel capable.
11:0 0h
RO Reserved (RSVD): Reserved.
4.22 Capabilities B (CAPID0)—Offset 48h
Control of bits in this register are only required for customer visible SKU differentiation.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits) Offset: [B:0, D:2, F:0] + 48h
31 2
8 2
4 2
0 1
6 1
2 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMGU_DIS RSVD SMT CACHESZ RSVD PLL_REF100_CFG PEGG3_DIS RSVD ADDGFXEN ADDGFXCAP RSVD DMIG3DIS RSVD GMM_DIS RSVD DMFC_DDR3 RSVD LPDDR3_EN RSVD
Range Bit
Default
Access and Field Name (ID): Description
31 0h RO_V
IMGU_DIS:
0: Device 5 associated memory spaces are accessible.
1: Device 5 associated memory and IO spaces are disabled by hardwiring the D1F2EN field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
30:29 0h RO
Reserved (RSVD): Reserved.
28 0h RO_V
SMT: This setting indicates whether or not the Processor is SMT capable.
27:25 0h
RO_V CACHESZ: This setting indicates the supporting cache sizes.
24:21 0h
RO Reserved (RSVD): Reserved.
20 0h RO_V
PEGG3_DIS: the processor: PCIe Gen 3 Disable.
0: Capable of running any of the Gen 3-compliant PEG controllers in Gen 3 mode (Devices 0/1/0, 0/1/1, 0/1/2)
1: Not capable of running any of the PEG controllers in Gen 3 mode 19 0h Reserved (RSVD): Reserved.
4.23 Device Enable (DEVEN0)—Offset 54h
Allows for enabling/disabling of PCI devices and functions that are within the Processor package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register.
All the bits in this register are Intel TXT Lockable.
Access Method
Default: 84BFh
15 0h RO_V
DMIG3DIS: DMI Gen 3 Disable.
14:9 0h RO
Reserved (RSVD): Reserved.
8 0h RO_V
GMM_DIS:
0: Device 8 associated memory spaces are accessible.
1: Device 8 associated memory and IO spaces are disabled by hardwiring the D8EN field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
7 0h RO
Reserved (RSVD): Reserved.
6:4 0h RO_V
DMFC_DDR3: This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored.
000: MC capable of DDR3 2667 (2667 is the upper limit) 001: MC capable of up to DDR3 2667
010: MC capable of up to DDR3 2400 011: MC capable of up to DDR3 2133 100: MC capable of up to DDR3 1867 101: MC capable of up to DDR3 1600 110: MC capable of up to DDR3 1333 111: MC capable of up to DDR3 1067 3 0h
RO Reserved (RSVD): Reserved.
2 0h
RO_V LPDDR3_EN: Allow LPDDR3 operation 1:0 0h
RO Reserved (RSVD): Reserved.
Range Bit
Default
Access and Field Name (ID): Description
Type: CFG
(Size: 32 bits) Offset: [B:0, D:2, F:0] + 54h
31 2
8 2
4 2
0 1
6 1
2 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1
RSVD D8EN D7EN D6EN RSVD D5EN RSVD D4EN RSVD D3EN D2EN 0EN 1EN 2EN D0EN
Range Bit
Default
Access and Field Name (ID): Description 31:16 0h
RO Reserved (RSVD): Reserved.
15 1h RO_V
D8EN:
0: Bus 0 Device 8 is disabled and not visible.
1: Bus 0 Device 8 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 8 capability is disabled.
14 0h RO_V
D7EN:
0: Bus 0 Device 7 is disabled and not visible.
1: Bus 0 Device 7 is enabled and visible.
Non-production BIOS code should provide a setup option to enable Bus 0 Device 7.
When enabled, Bus 0 Device 7 should be initialized in accordance to standard PCI device initialization procedures.
13 0h RO_V
D6EN: Reserved (RSVD):
12:11 0h RO
Reserved (RSVD): Reserved.
10 1h RO_V
D5EN:
0: Bus 0 Device 5 is disabled and not visible.
1: Bus 0 Device 5 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 5 capability is disabled.
9:8 0h RO
Reserved (RSVD): Reserved.
7 1h RO_V
D4EN:
0: Bus 0 Device 4 is disabled and not visible.
1: Bus 0 Device 4 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 4 capability is disabled.
6 0h
RO Reserved (RSVD): Reserved.
5 1h RO_V
D3EN:
0: Bus 0 Device 3 is disabled and hidden 1: Bus 0 Device 3 is enabled and visible
This bit will be set to 0b and remain 0b if Device 3 capability is disabled.
4 1h RO_V
D2EN:
0: Bus 0 Device 2 is disabled and hidden 1: Bus 0 Device 2 is enabled and visible
This bit will be set to 0b and remain 0b if Device 2 capability is disabled.
3 1h RO_V
D1F0EN:
0: Bus 0 Device 1 Function 0 is disabled and hidden.
1: Bus 0 Device 1 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG10 capability is disabled.
1h D1F1EN:
4.24 Base Data of Stolen Memory (BDSM)—Offset 5Ch
This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20).
Access Method
Default: 0h
4.25 Multi Size Aperture Control (MSAC)—Offset 62h
This register determines the size of the graphics memory aperture in function 0 and in the trusted space. Only the system BIOS will write this register based on pre- boot address allocation efforts, but the graphics may read this register to determine the correct aperture size. System BIOS needs to save this value on boot so that it can reset it correctly during S3 resume.
This register is Intel TXT locked, becomes read-only when trusted environment is launched.
Access Method
Default: 1h
Type: CFG
(Size: 32 bits) Offset: [B:0, D:2, F:0] + 5Ch
31 2
8 2
4 2
0 1
6 1
2 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDSM RSVD LOCK
Range Bit
Default
Access and Field Name (ID): Description
31:20 0h RO_V
BDSM: This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0, offset BC, bits 31:20).
19:1 0h
RO Reserved (RSVD): Reserved.
0 0h
RO_V LOCK: This bit will lock all writeable settings in this register, including itself.
Type: CFG
(Size: 8 bits) Offset: [B:0, D:2, F:0] + 62h
7 4 0
0 0 0 0 0 0 0 1
RSVDRW APSZ4 APSZ3 APSZ2 APSZ1 APSZ0
Range Bit
Default
Access and Field Name (ID): Description 7:5 0h
RW RSVDRW: Scratch Bits Only -- Have no physical effect on hardware
4 0h RW_KV
APSZ4: This field is used in conjunction with other APSZ* fields to determine the size of Aperture (GMADR) and affects certain bits of GMADR register. The description below is for all APSZ* fields 4:0
-00000 = 128MB => GMADR.B[26:4] is hardwired to 0 00001 = 256MB => GMADR.B[27] = 0, RO
00010 = illegal (hardware will treat this as 00011) 00011 = 512MB => GMADR.B[28:27] = 0, RO
0100-00110 = illegal (hardware will treat this as 00111) 00111= 1024MB => GMADR.B[29:27] = 0, RO 000-01110 = illegal (hardware will treat this as 01111) 01111= 2048MB => GMADR.B[30:27] = 0, RO
10000-11110 = illegal (hardware will treat this as 11111) 11111 = 4096MB => GMADR.B[31:27] = 0, RO
3 0h RW_KV
APSZ3: This field is used in conjuction with other APSZ* fields to determine the size of Aperture (GMADR) and affects certain bits of GMADR register. The description below is for all APSZ* fields 4:0
-00000 = 128MB => GMADR.B[26:4] is hardwired to 0 00001 = 256MB => GMADR.B[27] = 0, RO
00010 = illegal (hardware will treat this as 00011) 00011 = 512MB => GMADR.B[28:27] = 0, RO
0100-00110 = illegal (hardware will treat this as 00111) 00111= 1024MB => GMADR.B[29:27] = 0, RO 000-01110 = illegal (hardware will treat this as 01111) 01111= 2048MB => GMADR.B[30:27] = 0, RO
10000-11110 = illegal (hardware will treat this as 11111) 11111 = 4096MB => GMADR.B[31:27] = 0, RO
2 0h RW_KV
APSZ2: This field is used in conjuction with other APSZ* fields to determine the size of Aperture (GMADR) and affects certain bits of GMADR register. The description below is for all APSZ* fields 4:0
-00000 = 128MB => GMADR.B[26:4] is hardwired to 0 00001 = 256MB => GMADR.B[27] = 0, RO
00010 = illegal (hardware will treat this as 00011) 00011 = 512MB => GMADR.B[28:27] = 0, RO
0100-00110 = illegal (hardware will treat this as 00111) 00111= 1024MB => GMADR.B[29:27] = 0, RO 000-01110 = illegal (hardware will treat this as 01111) 01111= 2048MB => GMADR.B[30:27] = 0, RO
10000-11110 = illegal (hardware will treat this as 11111)