Default: 7FFFF00h
This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 15- 15-16MB
There can only be at most one MDA device in the system.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits) Offset: [B:0, D:0, F:0] + 86h
7 4 0
0 0 0 0 0 0 0 0
RSVD HIENABLE RSVD LOENABLE
Range Bit
Default
Access and Field Name (ID): Description 7:6 0h
RO Reserved (RSVD): Reserved.
5:4 0h RW_L
HIENABLE: This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh.
00: DRAM Disabled. All accesses are directed to DMI.
01: Read Only. All reads are sent to DRAM, all writes are forwarded to DMI.
10: Write Only. All writes are sent to DRAM, all reads are serviced by DMI.
11: Normal DRAM Operation. All reads and writes are serviced by DRAM.
3:2 0h RO
Reserved (RSVD): Reserved.
1:0 0h RW_L
LOENABLE: This field controls the steering of read and write cycles that address the BIOS area from 0E8000h to 0EBFFFh.
00: DRAM Disabled. All reads are sent to DRAM. All writes are forwarded to DMI.
01: Read Only. All reads are sent to DRAM. All writes are forwarded to DMI.
10: Write Only. All writes are sent to DRAM. All reads are serviced by DMI.
11: Normal DRAM Operation. All reads and writes are serviced by DRAM.
Type: CFG
(Size: 8 bits) Offset: [B:0, D:0, F:0] + 87h
7 4 0
0 0 0 0 0 0 0 0
HEN RSVD MDAP60 MDAP12 MDAP11 MDAP10
Range Bit
Default
Access and Field Name (ID): Description
7 0h RW
HEN: This field enables a memory hole in DRAM space. The DRAM that lies “behind”
this space is not remapped.
0: No memory hole.
1: Memory hole from 15MB to 16MB.
This bit is Intel TXT lockable.
6:4 0h RO
Reserved (RSVD): Reserved.
3 0h RW
MDAP60: This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of Processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1 function 2 VGA Enable bit is not set.
If device 1 function 2 VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range x3BCh-x3BFh are forwarded to PCI Express through device 1 function 2 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.
MDA resources are defined as the following:
Memory: 0B0h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP Description
0 0 All References to MDA and VGA space are not claimed by Device 1 Function 2.
0 1 Illegal combination
1 0 All VGA and MDA references are routed to PCI Express Graphics Attach device 1 function 2.
1 1 All VGA references are routed to PCI Express Graphics Attach device 1 function 2. MDA references are not claimed by device 1 function 2. VGA and MDA memory cycles can only be routed across PEG12 when MAE (PCICMD12[1]) is set. VGA and MDA I/O cycles can only be routed across PEG12 if IOAE (PCICMD12[0]) is set.
2 0h RW
MDAP12: This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of Processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1 function 2 VGA Enable bit is not set.
If device 1 function 2 VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range x3BCh-x3BFh are forwarded to PCI Express through device 1 function 2 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.
MDA resources are defined as the following:
Memory: 0B0h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP Description
0 0 All References to MDA and VGA space are not claimed by Device 1 Function 2.
0 1 Illegal combination
1 0 All VGA and MDA references are routed to PCI Express Graphics Attach device 1 function 2.
1 1 All VGA references are routed to PCI Express Graphics Attach device 1 function 2. MDA references are not claimed by device 1 function 2.
VGA and MDA memory cycles can only be routed across PEG12 when MAE (PCICMD12[1]) is set. VGA and MDA I/O cycles can only be routed across PEG12 if IOAE (PCICMD12[0]) is set.
1 0h RW
MDAP11: This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of Processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1 function 1 VGA Enable bit is not set.
If device 1 function 1 VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range x3BCh-x3BFh are forwarded to PCI Express through device 1 function 1 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.
MDA resources are defined as the following:
Memory: 0B0h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP Description
0 0 All References to MDA and VGA space are not claimed by Device 1 Function 1.
0 1 Illegal combination
1 0 All VGA and MDA references are routed to PCI Express Graphics Attach device 1 function 1.
1 1 All VGA references are routed to PCI Express Graphics Attach device 1 function 1. MDA references are not claimed by device 1 function 1.
VGA and MDA memory cycles can only be routed across PEG11 when MAE (PCICMD11[1]) is set. VGA and MDA I/O cycles can only be routed across PEG11 if IOAE (PCICMD11[0]) is set.
Range Bit
Default
Access and Field Name (ID): Description