5 Power Controller Unit (PCU) Register
5.4 Device 30 Function 3
5.4.1 CAP_HDR
This register is a Capability Header. It enumerates the CAPID registers available, and points to the next CAP_PTR.
5.4.2 CAPID0
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x80
Bit Attr Default Description 27:24 RO_FW 0x1 CAPID_Version:
This field has the value 0001b to identify the first revision of the CAPID register definition.
23:16 RO_FW 0x18 CAPID_Length:
This field indicates the structure length including the header in Bytes.
15:8 RO_FW 0x0 Next_Cap_Ptr:
This field is hardwired to 00h indicating the end of the capabilities linked list.
7:0 RO_FW 0x9 CAP_ID:
This field has the value 1001b to identify the CAPID assigned by the PCI SIG for vendor dependent capability pointers.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x84
Bit Attr Default Description 31:31 RO_FW 0x0 PCLMULQ_DIS:
PCLMULQ instruction disabled.
29:29 RO_FW 0x0 PECI_EN:
PECI to the Processor enabled.
26:26 RO_FW 0x0 GSSE256_DIS:
GSSE instructions disabled.
23:23 RO_FW 0x0 AES_DIS:
AES (Advanced Encryption Standard) disabled.
20:20 RO_FW 0x0 LT_SX_EN:
Intel TXT and FIT-boot enabled.
19:19 RO_FW 0x0 LT_PRODUCTION:
Intel TXT enabled.
18:18 RO_FW 0x0 SMX_DIS:
Intel TXT enabled.
17:17 RO_FW 0x0 VMX_DIS:
VMX (Virtual-Machine Extensions) disabled.
15:15 RO_FW 0x0 VT_X3_EN:
VT-x3 (Intel® Virtualization Technology) enabled.
12:12 RO_FW 0x0 HT_DIS:
Multithreading disabled.
5.4.3 CAPID1
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
11:9 RO_FW 0x0 LLC_WAY_EN:
Enable LLC ways value Cache size
'000: 0.5 M (4 lower ways) '001: 1 M (8 lower ways) '010: 1.5 M (12 lower ways) '011: 2 M (16 lower ways) '100: 2.5M (20 lower ways)
8:8 RO_FW 0x0 PRG_TDP_LIM_EN:
Usage of TURBO_POWER_LIMIT MSRs enabled.
4:4 RO_FW 0x0 DE_SKTR1_EX:
Set to 0 for Intel® Core™ i7 processor family for LGA2011-v3 Socket.
3:3 RO_FW 0x0 DE_SKTR_EP4S:
Set to 0 for Intel® Core™ i7 processor family for LGA2011-v3 Socket.
2:2 RO_FW 0x0 DE_SKTR_EP2S:
Indicates that device is a 2S SKU, independent of package.
1:1 RO_FW 0x0 DE_SKTB2_EN:
Set to 0 for Intel® Core™ i7 processor family for LGA2011-v3 Socket.
0:0 RO_FW 0x0 DE_SKTB2_UP:
Indicates that device is a UP SKU, independent of package.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x84
Bit Attr Default Description
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x88
Bit Attr Default Description
31:31 RO_FW 0x0 DIS_MEM_MIRROR:
Disable memory channel mirroring mode. In the mirroring mode, the server maintains two identical copies of all data in memory. The contents of branch 0 (containing channel 0/1) is duplicated in the DIMMs of branch 1 (containing channel 2/3). In the event of an uncorrectable error in one of the copies, the system can retrieve the mirrored copy of the data. The use of memory mirroring means that only half of the installed memory is available to the operating system.
30:30 RO_FW 0x0 DIS_MEM_LT_SUPPORT:
Intel TXT support disabled.
29:26 RO_FW 0x0 DMFC:
This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers. Any attempt to write an unsupported value will be ignored.
[3:3] - If set, over-clocking is supported and bits 2:0 are ignored.
[2:0] - Maximum allowed memory frequency.
3b110 - up to DDR-1333 (5 x 266) 3b101 - up to DDR-1600 (6 x 266) 3b100 - up to DDR-1866 (7 x 266) 3b011 - up to DDR-2133 (8 x 266) All others reserved
5.4.4 CAPID2
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU. Default value varies base on SKU.
25:23 RO_FW 0x0 MEM_PA_SIZE:
Physical address size supported in the core low two bits (uncore is 44 by default)
000: 46 010: 44 101: 36 110: 40 111: 39 reserved
8:8 RO_FW 0x0 rsvd
7:7 RO_FW 0x0 X2APIC_EN:
Extended APIC support enabled.
When set the enables the support of x2APIC (Extended APIC) in the core and uncore.
5:5 RO_FW 0x0 PWRBITS_DIS:
0b Power features activated during reset.
1b Power features (i.e. clock gating) are not activated.
4:4 RO_FW 0x0 GV3_DIS:
Intel SpeedStep® Technology disabled. Does not allow for the writing of the IA32_PERF_CTL register in order to change ratios.
1:1 RO_FW 0x0 CORE_RAS_EN:
Data Poisoning, MCA recovery enabled.
0:0 RO_FW 0x0 DCA_EN:
DCA (Direct Cache Access) enabled.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x88
Bit Attr Default Description
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x8c
Bit Attr Default Description
29:25 RO_FW 0x0 QPI_ALLOWED_CFCLK_RATIO_DIS:
Allowed Intel QPI link speeds.
bit 8 = 6.4GT/s bit 10 = 8.0GT/s bit 12 = 9.6GT/s 24:24 RO_FW 0x0 QPI_LINK1_DIS:
Intel QPI link 1 disabled.
23:23 RO_FW 0x0 QPI_LINK0_DIS:
Intel QPI link 0 disabled.
19:19 RO_FW 0x0 PCIE_DISNTB:
NTB (Non Transparent Bridge) support disabled.
18:18 RO_FW 0x0 PCIE_DISROL:
Raid-on-load disabled.
17:17 RO_FW 0x0 PCIE_DISLTSX:
Intel TXT disabled.
5.4.5 CAPID3
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
16:16 RO_FW 0x0 PCIE_DISLT:
Intel TXT disabled.
15:15 RO_FW 0x0 PCIE_DISPCIEG3:
PCIe Gen 3 disabled.
14:14 RO_FW 0x0 PCIE_DISDMA:
DMA engine and supporting functionality disabled.
13:13 RO_FW 0x0 PCIE_DISDMI:
DMI2 interface disabled.
12:3 RO_FW 0x0 PCIE_DISXPDEV:
Specific PCIe port disabled.
2:1 RO_FW 0x0 PCIE_DISx16:
PCIe x16 ports disabled (limit to x8's only).
0:0 RO_FW 0x0 PCIE_DISWS:
WS features such as graphics cards in PCIe slots disabled.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x8c
Bit Attr Default Description
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x90
Bit Attr Default Description
30:30 RO_FW 0x0 Reserved
29:24 RO_FW 0x0 Reserved
22:22 RO_FW 0x0 DISABLE_SMBUS_WRT:
SMBUS write capability disable control. When set, SMBus write is disabled.
21:21 RO_FW 0x0 DISABLE_ROL_OR_ADR:
RAID-On-LOAD disable control. When set, memory ignores ADR event.
Download may change the default value after reset de-assertion.
20:20 RO_FW 0x0 DISABLE_EXTENDED_ADDR_DIMM:
Extended addressing DIMM disable control. When set, DIMM with extended addressing (MA[17/16] is forced to be zero when driving MA[17:16]).
19:19 RO_FW 0x0 DISABLE_EXTENDED_LATENCY_DIMM:
Extended latency DIMM disable control. When set, DIMM with extended latency is forced to CAS to be less than or equal to 14.
18:18 RO_FW 0x0 DISABLE_PATROL_SCRUB:
Patrol scrub disable control. When set, rank patrol scrub is disabled.
17:17 RO_FW 0x0 DISABLE_SPARING:
Sparing disable control. When set, rank sparing is disabled.
16:16 RO_FW 0x0 DISABLE_LOCKSTEP:
LOCKSTEP disable control. When set, channel lockstep operation is disabled.
15:15 RO_FW 0x0 DISABLE_CLTT:
CLTT disable control. When set, CLTT support is disabled by disabling TSOD polling.
5.4.6 CAPID4
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
14:14 RO_FW 0x0 DISABLE_UDIMM:
UDIMM disable control. When set, UDIMM support is disabled by disabling address bit swizzling.
13:13 RO_FW 0x0 DISABLE_RDIMM:
RDIMM disable control. When set, RDIMM support is disabled.
12:12 RO_FW 0x0 DISABLE_3N:
3N disable control. When set, 3N mode under normal operation (excluding MRS) is disabled.
11:11 RO_FW 0x0 DISABLE_DIR:
DIR disable control. When set, directory is disabled.
10:10 RO_FW 0x0 DISABLE_ECC:
ECC disable control. When set, ECC is disabled.
9:9 RO_FW 0x0 DISABLE_QR_DIMM:
QR DIMM disable control. When set, CS signals for QR-DIMM in slot 0-1 is disabled.
8:8 RO_FW 0x0 DISABLE_4GBIT_DDR:
4 GB disable control. When set, the address decode to the corresponding 4 Gb mapping is disabled.
7:7 RO_FW 0x0 DISABLE_8GBIT_DDR:
8 Gb or higher disable control. When set, the address decode to the corresponding 8 Gb or higher mapping is disabled.
5:5 RO_FW 0x0 DISABLE_3_DPC:
3 DPC disable control. When set, CS signals for DIMM slot 2 are disabled.
4:4 RO_FW 0x0 DISABLE_2_DPC:
2 DPC disable control. When set, CS signals for DIMM slot 1-2 (i.e. slots 0 is not disabled) are disabled.
3:0 RO_FW 0x0 CHN_DISABLE:
Channel disable control. When set, the corresponding memory channel is disabled.
1 IMC and HA on SKU:
• 0000 = Channels 0/1/2/3 enabled
• 0001 = Channels 1/2/3 enabled, Channel 0 disabled
• 1100 = Channels 0/1 enabled, Channels 2/3 disabled 2 IMC and HA on SKU:
• 0000 = Channels 0/1/2/3 enabled (EP with 4 channels)
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x90
Bit Attr Default Description
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x94
Bit Attr Default Description
31:31 RO_FW 0x0 Disable DRAM Power Meter (DRAM_POWER_METER_DISABLE) 30:30 RO_FW 0x0 Disable DRAM RAPL(DRAM_RAPL_DISABLE)
26:26 RO_FW 0x0 EET_ENABLE:
Energy efficient turbo enabled.
5.4.7 CAPID5
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
5.4.8 CAPID6
This register is a Capability Register used to expose feature support for BIOS use.
Default value varies base on SKU.
25:25 RO_FW 0x0 PCPS_DISABLE:
Per-core P-state disabled.
24:24 RO_FW 0x0 UFS_DISABLE:
UFS (Uncore Frequency Scaling) disabled.
19:19 RO_FW 0x0 ENHANCED_MCA_DIS:
Enhanced MCA disabled
14:14 RO_FW 0x0 FMA_DIS:
FMA (Floating point Multiple Add) instructions disabled.
7:6 RO_FW 0x0 PHYSICAL:
Physical configuration of processor.
10:configuration 2; 01:configuration 1; 00:configuration 0;
5:4 RO_FW 0x0 PROD_TYPE — Product type
00 = Intel® Core™ i7 processor family for LGA2011-v3 Socket
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x94
Bit Attr Default Description
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x98
Bit Attr Default Description
31:31 RO_FW 0x0 COD_ENABLE:
COD (Cluster on die) support enabled where the processor clusters cores to the near memory controller.
30:30 RO_FW 0x0 HITME_ENABLE : Directory Cache enabled.
24:24 RO_FW 0x0 HSW_NI_DIS
New instructions except LZCNT, TZCNT, MOVBE disabled which Intel® Core™ i7 processor family for LGA2011-v3 Socket disabled.
17:0 RO_FW 0x0 LLC_SLICE_EN:
Enabled Cbo slices (Cbo with enabled LLC slice).
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x9C
Bit Attr Default Description 30:30 RO_FW 0x0 IIO_LLCCONFIG_EN:
IIO to allocate in LLC enabled.
5.4.9 SMT_CONTROL
5.4.10 RESOLVED_CORES
§
29:29 RO_FW 0x0 DE_SKT_SECONDHA:
Indicates when second Home Agent and Memory Controller is enabled.
17:0 RO_FW 0x0 LLC_IA_CORE_EN:
Cores enabled on SKU of the Intel® Core™ i7 processor family for LGA2011-v3 Socket.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0xb0
Bit Attr Default Description 24:24 RO_V 0x0 SMT Capability:
Enabled threads in the package.
0b 1 thread 1b 2 threads
9:8 RO_V 0x0 Thread Mask (THREAD_MASK):
Thread Mask indicates which threads are enabled in the core. The LSB is the enable bit for Thread 0, whereas the MSB is the enable bit for Thread 1.
This field is determined by FW based on CSR_DESIRED_CORES[SMT_DISABLE]
and SKU capability.
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0xb4
Bit Attr Default Description
17:0 RO_V 0x0 CORE_MASK — The resolved IA core mask contains the functional (enabled in SKU) and non-defeatured IA cores.
The mask is indexed by logical ID. It is normally contiguous, unless BIOS defeature is activated on a particular core.
BSP and APIC IDs will be set by the processor based on this value.
This field is determined by FW based on CSR_DESIRED_CORES[CORE_OFF_MASK].
Type: CFG Port ID: N/A
Bus: 1 Device: 30 Function: 3
Offset: 0x9C
Bit Attr Default Description