The code-phase state counter is done more or less the same as done in the GPS100SC receiver except it records to a ½ chip resolution. This is a linear counter whose contents reflect the Code State in ½ chip increments. This is latched by TIC (typically, every 1/10 s) and can be read by the host computer. This has a time resolution of one C/A code chip or about ½ms. This is of course is the 1 ms dial of the replica clock with twice as many increments (2,046 total ) compared to the GPS100SC version (1,023 total).
Additionally, the phase register of the code-clock DCO can be recorded at the TIC time signal. The DCO phase register resolution is very high at 1/2,048 of a chip. This works out to be a time resolution of about 0.5 ns. In the GPS100SC receiver, we had 20 increments on the 0.977 ms dial. The GP2021 has 1,024 increments on a 0.488 ms dial! Figure 9.5 shows the GP2021 replica clock. In theory, the GP2021 can resolve down to about 0.15 m. But jitter in the C/A code loop and other uncertainties insure this accuracy will not be achieved in the range measurement with just C/A code measurements, see Chap. 8.
capacity of32,768. In use, the probability that theþ6 would be applied over one 1 ms would be zero. We can say the register is big enough.
Now that we know the details of operation, we need to look at the function this accumulation operation performs.
9.3.2 The DUMP Signal
The digital accumulators are reset to zero by this signal as we just learned. This signal corresponds exactly to the C/A epoch signal, which occurs at a nominal rate of 1 kHz. Therefore, the DUMP signals for each channel are different and will not
0
0 20MSEC
1 TIC = 1MSEC ( 20 TICS TOTAL)
0 1MSEC
1 TIC =0.488uSEC (2046 TICS TOTAL)
Wc
Wd
20MSEC 100MSEC
200MSEC
300MSEC
400MSEC 600MSEC
700MSEC 800MSEC
900MSEC
0 1 SEC
1 TIC = 20MSEC
Ws
(50 TICS TOTAL)
GPSEC_CNT 604784 SECONDS (1 WEEK)
0 0.488USEC
(1024 TICS TOTAL) 1 TIC = 0.477NSEC
Wm
Fig. 9.5 SV replica clock model for GP2021
9.3 The 16-Bit Accumulators 177
be synchronous with each other, unless two channels are set to receive the same SV signal. The DUMP signal not only resets the accumulator to zero but also resets the Code-Phase Counter to zero and Resets the Code Generator to its “initial” state.
By tying the DUMP signal to the 1 kHz C/A epoch, the effect is to synchronize the integration period to the timing of the incoming GPS signal. Of course, this statement is only true once signal TRACK is achieved. Assuming tracking is achieved, the integrators will start at the beginning of C/A code cycle and reset at its end. Also, there will be exactly 20 integration periods for each data bit.
9.3.3 Digital Accumulators as Integrators
The action of digital accumulation is closely related to integration. Integration is inherently a smoothing or averaging operation when we think of its effects on an applied signal. Knowing this, we can say that the accumulators perform signal smoothing and averaging. But we can go further and state that digital integrators that are cleared (or DUMPED) at regular intervals of time act like a lowpass filter with a cutoff frequency of about half the DUMP frequency.
9.3.4 Approximating a Digital Accumulator as Analog Lowpass Filter
To understand the lowpass approximation, examine Fig.9.6. This figure shows the contents of the accumulator as a function of time for two sinewave inputs. For this example, assume that the sample rate is lower than actually used so as to show the
“steps” in the accumulation and that the input resolution (in bits) is fairly high.
In the first case, the sinewave has a frequency of 100 Hz. For convenience, the DUMP period is shown synchronous with the sinewave and starts at the beginning of the sinewave for both input examples of Fig. 9.6. We see the accumulator contents rising and then being cleared every 1 ms. Since there are ten 1 ms intervals in a 100 Hz sinewave, the accumulator is dumped ten times.
Looking at the resulting accumulator output one could say it is not doing much smoothing, in fact it is a saw tooth-like waveform and rough. But it is also apparent that the peak value of accumulator contents are following the amplitude of the sinewave. So in some sense the accumulator contents can be seen as a sinewave.
Now let us look at the case where a sinewave of exactly 1 kHz is applied to the accumulator input. Now what happens is the accumulator contents rise to a maxi-mum at the point where the sinewave goes from positive to negative. Then the contents of the accumulator start decreasing as we are now subtracting values, as the signal is negative in value. At the end of the applied 1 kHz sinewave period, the accumulator contents are zero.
178 9 The Zarlink 12-Channel GPS Receiver
1KHZSINEWAVEANDINTEGRATORCONTENTSASFUNCTIONOFTIME,INTEGRATORVALUE@DUMP=0
100HzSINEWAVEANDINTEGRATORCONTENTSASAFUNCTIONOFTIME 00 1MSEC DUMP2MSEC DUMP3MSEC DUMP4MSEC DUMPTIME TIME
DUMP 6MSECDUMP 7MSECDUMP 8MSECDUMP 9MSECDUMP 10MSEC Fig.9.6Accumulatorcontentsasfunctionoftimewithsinewave-appliedintegrationinterval(sampleclock)nottoscale
9.3 The 16-Bit Accumulators 179
Now we can say that for a digital accumulator, with a DUMP cycle of 1 ms and input sinewaves with frequencies above 1 kHz, theaverageresults in accumulator contents are zero. And we can say that for sinewaves with frequencies below about 500 Hz, theaverageresult in the accumulator follows the amplitude of the applied sinewave. It should be clear now that the digital accumulators in the GP2021 are acting like lowpass filters with a cutoff frequency of about 500 Hz.