5.6 8259 Programmable Interrupt Controllers (PIC) (D31:F0)
5.15 Intel ® Rapid Storage Technology (Intel ® RST) ConfigurationConfiguration
Intel® RST offers several diverse options for RAID (redundant array of independent disks) to meet the needs of the end user. AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in the PCH SATA controller.
• RAID Level 0 performance scaling up to 6 drives, enabling higher throughput for data intensive applications, such as video editing.
• Data redundancy is offered through RAID Level 1 that performs mirroring.
• RAID Level 10 provides high levels of storage performance with data protection, combining the fault-tolerance of RAID Level 1 with the performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems that require both performance and fault-tolerance. RAID Level 10 requires 4 hard drives, and provides the capacity of two drives.
• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance.
By using the PCH built-in Intel® Rapid Storage Technology, there is no loss of additional PCIe*/system resources or add-in card slot/motherboard space footprint used,
compared to when a discrete RAID controller is implemented. Intel® Rapid Storage Technology functionality requires the following:
• PCH SKU enabled for Intel® Rapid Storage Technology (see Section 2.3)
• Intel® Rapid Storage Technology RAID Option ROM must be on the platform
• Intel® Rapid Storage Technology drivers, most recent revision.
• At least two SATA hard disk drives (minimum depends on RAID configuration).
Intel® Rapid Storage Technology is not available in the following configurations:
• The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset 9Ch bit 7) is set to 1.
Functional Description
5.15.0.1 Intel® Rapid Storage Technology (Intel® RST) RAID Option ROM The Intel® Rapid Storage Technology RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions:
• Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create and delete RAID volumes and select recovery options when problems occur.
• Provides boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by MS-DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order.
• At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I.
5.15.1 Intel
®Smart Response Technology (Intel
®RST)
Part of the Intel® RST storage class driver feature set, Intel® Smart Response
Technology implements storage I/O caching to provide users with faster response times for things like system boot and application startup. On a traditional system,
performance of these operations is limited by the hard drive, particularly when there may be other I/O intensive background activities running simultaneously, such as system updates or virus scans. Intel® Smart Response Technology accelerates the system response experience by putting frequently-used blocks of disk data on an SSD, providing dramatically faster access to user data than the hard disk alone can provide.
The user sees the full capacity of the hard drive with the traditional single drive letter with overall system responsiveness similar to what an SSD-only system provides.
See Section 1.3 for SKUs enabled for Intel® Smart Response Technology.
5.15.2 Power Management Operation
Power management of the PCH SATA controller and ports will cover operations of the host controller and the SATA link.
5.15.2.1 Power State Mappings
The D0 PCI power management (PM) state for a device is supported by the PCH SATA controller.
SATA devices may also have multiple power states. SATA adopted three main power states from parallel ATA. The three device states are supported through ACPI. They are:
• D0 – Device is working and instantly available.
• D1 – Device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds
• D3 – From the SATA device’s perspective, no different than a D1 state, in that it is entered using the STANDBY IMMEDIATE command. However, an ACPI method is also called that will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Finally, the SATA specification defines three PHY layer power states that have no equivalent mappings to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and in active state
• Partial – PHY logic is powered up, and in a reduced power state. The link PM exit latency to active state maximum is 10 ns.
• Slumber – PHY logic is powered up, and in a reduced power state. The link PM exit latency to active state maximum is 10 ms.
• Devslp – PHY logic is powered down. The link PM exit latency from this state to active state maximum is 20 ms, unless otherwise specified by DETO in Identify Device Data Log page 08h (see 13.7.9.4 of the SATA Revision 3.2 Gold
specification).
Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller specification defines these states as sub-states of the device D0 state.
5.15.2.2 Power State Transitions
5.15.2.2.1 Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would be most analogous to CLKRUN# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. The SATA controller defines PHY layer power management (as performed using primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side.
The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed.
When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COMWAKE to bring the link back online. Similarly, the SATA device must perform the same COMWAKE action.
5.15.2.2.2 Devslp State Entry/Exit
Devslp is a host-controlled hardware signal that enables a SATA host and device to enter an ultra-low interface power state, including the possibility of completely powering down the host and device PHYs.
5.15.2.2.3 Device D1 and D3 States
These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other than sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
5.15.2.2.4 Host Controller D3HOT State
After the interface and device have been put into a low-power state, the SATA host controller may be put into a low-power state. This is performed using the PCI power management registers in configuration space. There are two very important aspects to Note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort.
Functional Description
2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized.
When returning from a D3 state, an internal reset will not be performed.
5.15.2.3 Low Power Platform Consideration
When the low power feature is enabled, the Intel SATA controller may power off PLLs or OOB detection circuitry while in the Slumber link power state. As a result, a device initiated wake may not be recognized by the host. For example, when the low power feature is enabled it can prevent a Zero Power ODD (ZPODD) device from successfully communicating with the host on media insertion.
Note: Refer to PHYDPGE of the SCLKGC2 register for details.
5.15.3 SATA Device Presence
The flow used to indicate SATA device presence is shown in Figure 5-10. The ‘PxE’ bit refers to PCS.P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set, a device is present; if the bit is cleared, a device is not present. If a port is disabled, software can check to see if a new device is connected by periodically re-enabling the port and observing if a device is present. If a device is not present, it can disable the port and check again later. If a port remains enabled, software can periodically poll PCS.PxP to see if a new device is connected.
Figure 5-10. Flow for Port Enable/Device Present Bits
5.15.4 SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port.
SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive.
5.15.5 Advanced Host Controller Interface (AHCI) Operation
The PCH SATA controller provides hardware support for the Advanced Host Controller Interface (AHCI)—a programming interface for SATA host controllers developed through a joint industry effort. AHCI defines transactions between the SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware assisted native command queuing. AHCI also provides usability enhancements, such as hot-plug. AHCI requires appropriate software support (such as, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware.
The PCH SATA controller supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface Specification, Revision 1.3 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and hot-plug through the use of interlock switch support. Additional platform hardware and software may be required depending on the implementation.
Note: For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
5.15.6 External SATA
The PCH SATA controller supports external SATA. External SATA uses the SATA interface outside of the system box. The usage model for this feature must comply with the Serial ATA II (SATA Gen 2, 3Gb/s) Cables and Connectors Volume 2 Gold specification at:
www.sata-io.org. Intel® validates one configuration:
• The back-panel solution involves running a trace to the I/O back panel and connecting a device using an external SATA connector on the board.