3 Platform Controller Hub (PCH) Pin States
3.2 Output and I/O Signals Planes and States
Table 3-2 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used:
“DL” PCH drives low
“DH” PCH drives high
“IPU” Internal pull-up
“IPD” Internal pull-down
“T” Toggling or signal is transitioning because function is not stopping.
“High-Z” Tri-state—PCH not driving the signal high or low
“Defined” Driven to a level that is defined by the function or external pull-up/pull-down resistor (will be high or low).
“Off” The power plane is off; PCH is not driving when configured as an output or sampling when configured as an input.
Note: Pin state within table assumes interfaces are idle and default pin configuration for different power states.
Signal levels are the same in S3, S4, and S5, except as noted.
PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# de-assertion. Some signals are determinate and defined prior to RSMRST#
de-assertion; refer to signals with Note 21 references.
PCH core well signal states are indeterminate and undefined and may glitch prior to PCH_PWROK assertion.
DSW indicates PCH Deep Sx Well. This state provides a few wake events and critical context to allow system to draw minimal power in S3, S4, or S5 states. PCH DSW well signal states are indeterminate and undefined and may glitch prior to DPWROK assertion. Some signals are determinate and defined prior to DPWROK assertion; refer to signals with Note 21 references.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated with active usage models while the host system is in Sx. These are signals on VCCSPI.
Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 1 of 5)
Signal Name Power Plane During Reset1 Immediately
After Reset1 S3/S4/S5 Deep Sx USB Interface
USB2n[7:0], USB2p[7:0] DSW IPD IPD IPD IPD
USB3Tn[2:1],
USB3Tp[2:1] Suspend IPD IPD27 S3 IPD27
S4/S5 Off Off USB3Tn[4:3],
USB3Tp[4:3]19 Suspend IPD IPD27 S3 IPD27
S4/S5 Off Off
USBRBIAS Core High-Z High-Z Off Off
Platform Controller Hub (PCH) Pin States
PCI Express*
PETp[2:1], PETn[2:1]19 Suspend IPD27 IPD27 Off Off
PETp[4:3], PETn[4:3] Core IPD27 IPD27 Off Off
PETp5_L[3:0], PETn5_L[3:0] Core IPD27 IPD27 Off Off
PETp6_L[3:0], PETn6_L[3:0] Core IPU IPU Off Off
SATA Interface SATA_TXP[3:0],
SATA_TXN[3:0] Core IPU IPU Off Off
SATALED# Core High-Z High-Z Off Off
DEVSLP0/GPIO3322 Core High-Z High-Z Off Off
DEVSLP1/GPIO3822 Core High-Z High-Z Off Off
DEVSLP2/GPIO3922 Core High-Z High-Z Off Off
Clocking Signals CLKOUT_ITPXDP_P,
CLKOUT_ITPXDP_N Core T T Off Off
XTAL24_OUT Core High-Z High-Z Off Off
DIFFCLK_BIASREF Core High-Z High-Z Off Off
CLKOUT_PCIE[5:0] P,
CLKOUT_PCIE[5:0] N Core T T Off Off
CLKOUT_LPC[1:0] P10,
CLKOUT_LPC[1:0] N10 Core T T Off Off
PCIECLKRQ[5:0]#/
GPIO[23:18]22 Core High-Z High-Z Off Off
Interrupts
PIRQ[A:D]#/GPIO[80:77]22 Core High-Z High-Z Off Off
SERIRQ Core High-Z High-Z Off Off
Backlight Control Signals
eDP_VDD_EN Core DL DL/High-Z18 Off Off
eDP_BKLTEN Core DL DL/High-Z18 Off Off
eDP_BKLTCTL Core DL DL/High-Z18 Off Off
Digital Display Interface DDP[C:B]_AUXP,
DDP[C:B]_AUXN Core IPD IPD Off Off
eDP_AUXP, eDP_AUXN Core IPD IPD Off Off
DDPB_CTRLCLK,
DDPC_CTRLCLK Core High-Z High-Z Off Off
DDPB_CTRLDATA6
DDPC_CTRLDATA6 Core IPD12 High-Z Off Off
LPC/FWH Interface
LAD[3:0] Core IPU IPU Off Off
LFRAME# Core DH DH Off Off
Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 2 of 5)
Signal Name Power Plane During Reset1 Immediately
After Reset1 S3/S4/S5 Deep Sx
SMBus Interface
SMBCLK, SMBDATA Suspend High-Z High-Z High-Z Off
System Management Interface
SMBALERT#/ GPIO1122 Suspend High-Z High-Z High-Z Off
SML0DATA Suspend High-Z High-Z High-Z Off
SML0CLK Suspend High-Z High-Z High-Z Off
SML0ALERT#/ GPIO6022 Suspend High-Z High-Z High-Z Off
SML1CLK/GPIO7522 Suspend High-Z High-Z High-Z Off
SML1ALERT#/TEMP_ALERT#/
GPIO7322 Suspend High-Z High-Z High-Z Off
SML1DATA/GPIO7422 Suspend High-Z High-Z High-Z Off
Controller Link
CL_CLK7 Suspend IPD8 IPD8 IPU/IPD Off
CL_DATA7 Suspend IPD8 IPD8 IPU/IPD Off
CL_RST#7 Suspend DL DH DH Off
SPI Interface
SPI_CLK ASW High-Z23 DL DL Off
SPI_CS0# ASW High-Z23 DH DH Off
SPI_CS1# ASW High-Z23 DH DH Off
SPI_CS2# ASW High-Z23 DH DH Off
SPI_MOSI ASW High-Z23 DL DL Off
SPI_MISO ASW High-Z23 IPU IPU Off
SPI_IO2 ASW High-Z23 IPU IPU Off
SPI_IO3 ASW High-Z23 IPU IPU Off
Power Management
CLKRUN#/GPIO3222 Core High-Z High-Z Off Off
HSIOPC/GPIO7128 Core DH DH Off Off
SM_DRAMRST#21 DSW DL High-Z High-Z High-Z
WAKE# DSW High-Z High-Z High-Z High-Z/
IPD34
PME# Suspend IPU IPU IPU Off
PLTRST# Suspend DL DH DL Off
SLP_S0#21 Suspend DH DH DH Off
SLP_A#21 DSW DL DH DH13 DL
SLP_S3#21 DSW DL DH DL DL
SLP_S4#21 DSW DL DH DL/DH20 DL/DH30
SLP_S5#/GPIO6311,21,28 DSW DL DH DL/DH2 DL/DH30
SUS_STAT#/GPIO6121,28,32 Suspend DL DH17 DL Off
SUSCLK/GPIO6221,28 Suspend DL T Off
SLP_SUS#21 DSW DL DH DH DL
Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 3 of 5)
Signal Name Power Plane During Reset1 Immediately
After Reset1 S3/S4/S5 Deep Sx
Platform Controller Hub (PCH) Pin States
SUSWARN#/
SUSPWRDNACK/
GPIO3021,24,26,28 Suspend DL DL DL5 N/A
SUSWARN#/SUSPWRDNACK/
GPIO3021,25,26,28 Suspend DL DL DL Off
LAN_PHY_PWR_CTRL/
GPIO1211,21,28 DSW DL DL DL DL
SLP_LAN#21 DSW DL DL DL/DH33 DL/DH33
SLP_WLAN#/
GPIO2911,14,21,28 DSW DL DL33 DL/DH33 DL33
Miscellaneous Signals
SPKR/GPIO816,22 Core IPD DL Off Off
Intel® High Definition Audio (Intel® HD Audio) Interface
HDA_RST#/I2S_MCLK Suspend/Core DL DL3 DL29 Off
HDA_SDO4,6/I2S0_TXD Suspend/Core IPD IPD IPD29 Off
HDA_SYNC6/I2S0_SFRM Suspend/Core IPD IPD IPD29 Off
HDA_BCLK/I2S0_SCLK Suspend/Core DL DL3 DL29 Off
HDA_DOCK_EN#/I2S1_TXD Suspend/Core DH DH16 DH16,29 Off
HDA_DOCK_RST#/
I2S1_SFRM Suspend/Core DL DL9 DL9,29 Off
I2S Interface
HDA_RST#/I2S_MCLK Suspend/Core DL DL DL29 Off
HDA_SDO/I2S0_TXD7 Suspend/Core IPD IPD IPD29 Off
HDA_SYNC/I2S0_SFRM Suspend/Core IPD IPD IPD29 Off
HDA_BCLK/I2S0_SCLK Suspend/Core DL DL3 DL29 Off
HDA_DOCK_EN#/I2S1_TXD Suspend/Core DH DH DH29 Off
HDA_DOCK_RST#/
I2S1_SFRM Suspend/Core DL DL DL29 Off
I2S1_SCLK Suspend/Core DL DL DL29 Off
General Purpose SPI Interface
GSPI0_CS#/GPIO8322 Core High-Z High-Z Off Off
GSPI0_CLK#/GPIO8422 Core High-Z High-Z Off Off
GSPI0_MOSI/GPIO866,22 Core IPD DL Off Off
GSPI1_CS#/GPIO8722 Core High-Z High-Z Off Off
GSPI1_CLK#/GPIO8822 Core High-Z High-Z Off Off
GSPI1_MOSI/GPIO9022 Core High-Z High-Z Off Off
UART Interface
UART0_TXD/GPIO9222 Core High-Z High-Z Off Off
UART0_RST#/GPIO9322 Core High-Z High-Z Off Off
UART1_TXD/GPIO122 Core High-Z High-Z Off Off
UART1_RST#/GPIO222 Core High-Z High-Z Off Off
Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 4 of 5)
Signal Name Power Plane During Reset1 Immediately
After Reset1 S3/S4/S5 Deep Sx
Notes:
1. The states of signals on Core power planes are evaluated at the times during PLTRST# and immediately after PLTRST#. The states of the Controller Link signals are taken at the times during CL_RST# and immediately after CL_RST#. The states of the Suspend signals are evaluated at the times during RSMRST#
and immediately after RSMRST#, with an exception to GPIO signals; refer to Section 2.24 for more details on GPIO state after reset. The states of the HDA signals are evaluated at the times during HDA_RST# and immediately after HDA_RST#. The states of signals on DSW power planes are evaluated at times during DPWROK and immediately after DPWROK assertion.
2. SLP_S5# signal will be driven high in the S3 and S4 state and driven low in the S5 state.
I2C Interface
I2C0_SDA/GPIO422 Core High-Z High-Z Off Off
I2C0_SCL/GPIO522 Core High-Z High-Z Off Off
I2C1_SDA/GPIO622 Core High-Z High-Z Off Off
I2C1_SCL/GPIO722 Core High-Z High-Z Off Off
SDIO Interface
SDIO_CLK/GPIO6422 Core High-Z High-Z Off Off
SDIO_CMD/GPIO6522 Core High-Z High-Z Off Off
SDIO_D0/GPIO666,22 Core IPD DL Off Off
SDIO_D[3:1]/GPIO[69:67]22 Core High-Z High-Z Off Off
SDIO_POWER_EN/GPIO7022 Core High-Z High-Z Off Off
Multiplexed GPIO Signals (Defaults to Native Mode) Used as GPIO
HSIOPC/GPIO7132 Core DH DH Off Off
SLP_S5#/GPIO6311,21,32 DSW DL DH High-Z High-Z
SUS_STAT#/GPIO6121,32 Suspend DL DH17 High-Z Off
SUSCLK/GPIO6221,32 Suspend DL T High-Z Off
SUSWARN#/SUSPWRDNACK/
GPIO3021,26,32 Suspend DL DL High-Z N/A
LAN_PHY_PWR_CTRL/
GPIO1211,21,32 DSW DL DL High-Z High-Z
SLP_WLAN#/
GPIO2911,14,21,32 DSW DL DL High-Z High-Z
BATLOW#/GPIO7232 DSW High-Z High-Z High-Z High-Z
Multiplexed GPIO Signals (Defaults to GPO)
SDIO_D0/GPIO666,32 Core IPD DL Off Off
SPKR/GPIO816,32 Core IPD DL Off Off
GSPI0_MOSI/GPIO866,32 Core IPD DL Off Off
UnMultiplexed GPIO Signals (Defaults to GPO)
GPIO156,32 Suspend IPD DL DL Off
Testability
PCH_TDO Suspend High-Z High-Z High-Z Off
PCH_TDI Suspend IPU IPU IPU Off
PCH_TMS Suspend IPU IPU IPU Off
PCH_TCK Suspend IPD IPD IPD Off
Table 3-2. Power Plane and States for Output and I/O Signals for Configurations (Sheet 5 of 5)
Signal Name Power Plane During Reset1 Immediately
After Reset1 S3/S4/S5 Deep Sx
Platform Controller Hub (PCH) Pin States
3. Internal pull-down enabled when PCH_PWROK de-asserts until Intel® High Definition Audio Controller Reset bit is set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BCLK will start to toggle.
4. Internal pull-down on HDA_SDO enabled during reset.
5. Pin state always driven low during S0 or Sx/M3. In Sx/M-Off, pin may be driven low or high based on Intel® ME policy.
6. This signal is sampled as a functional strap During Reset. Refer to Functional straps definition table for usage.
7. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive a logical 1 or 0.
8. I/O buffer pull-down is enabled.
9. This pin will be driven to high when Dock Attach bit is set (Docking Control Register D27:F0 Offset 4Ch).
10. The pull-down is disabled after the pins are driven strongly to 0 when PCH_PWROK is asserted.
11. Native/GPIO functionality controlled using soft straps. Default to Native functionality until soft straps are loaded.
12. External 2.2 K pull-up when used.
13. The SLP_A# state will be determined by Intel® ME policies.
14. SLP_WLAN# behavior after reset is dependent on value of SLP_WLAN# default value bit. A soft strap is used to select between SLP_WLAN# and GPIO usage. When strap is set to 0 (default), pin is used as SLP_WLAN#, when soft strap is set to 1, pin is used as GPIO29.
15. Soft straps are handled through FITc .
16. This pin will be driven low when Dock Attach bit is set (Docking Control Register D27:F0 Offset 4Ch).
17. Driven high after PCH_PWROK rises.
18. Pins are tri-stated when eDP is disabled.
19. USB 3.0 or PCIe* mode selection is based on soft strap.
20. SLP_S4# signal will be driven high in the S3 state and driven low in the S4 and S5 state.
21. The pin requires glitch-free output power sequence. The pull-down is momentarily when the corresponding buffer power supply is not stable.
22. Pin defaults to GPIO mode. The pin state during and immediately after reset follows default GPIO mode pin state. The pin state for S0 to Deep Sx reflects assumption that GPIO Use Select register was programmed to native mode functionality. If GPIO Use Select register is programmed to GPIO mode, refer to Multiplexed GPIO (Defaults to GPIO Mode) section for the respective pin states in S0 to Deep Sx.
23. Pins are tri-stated prior to RSMRST# de-assertion.
24. Pin-state indicates SUSPWRDNACK in Non-Deep Sx, Deep Sx after RTC power failure.
25. Pin-state indicates SUSWARN# in Deep Sx supported platforms.
26. SUSPWRDNACK is the default mode of operation. If system supports Deep Sx, subsequent boots will default to SUSWARN#
27. This is a strong pull low.
28. Pin defaults to native mode. The pin state during and immediately after reset follows default native mode pin state. The pin state for S0 to Deep Sx reflects assumption that GPIO Use Select register was kept at native mode functionality. If GPIO Use Select register is programmed to GPIO mode, refer to Multiplexed GPIO (Defaults to Native Mode) section for the respective pin states in S0 to Deep Sx.
29. Buffer is off if connected to Core power.
30. When platform enters Deep Sx, pin will retain the value held prior to Deep Sx entry. If platform was in S5 prior to Deep Sx, SLP_S3#, SLP_S4#, SLP_S5# will be asserted. If platform was in S4 prior to Deep Sx, SLP_S3# and SLP_S4# will be asserted while SLP_S5# will be de-asserted.
31. N/A
32. Internal weak pull resistor is default off but configurable (pull-up/pull-down/none) after boot. The pin may be IPD or IPU depending on configuration by means of the GPIO register settings.
33. Pin may toggle from RSMRST# de-assertion to PLTRST# de-assertion due to Intel® ME. Based on wake events and Intel® ME state/policy.
34. Based on configuration, pin maybe High-Z or IPD.
35. Not all signals or pin functionalities may be available on a given SKU. See Section 2.3 and Chapter 2 for details.