Intel ® 300 Series and Intel ® C240 Series Chipset Family Platform

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Intel ® 300 Series and Intel ® C240 Series Chipset Family Platform

Controller Hub

Datasheet – Volume 1 of 2 Revision 006

September 2019

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Revision History

Revision Number Description Revision Date

001 • Initial Release April 2018

002 Chapter 10, Electrical Characteristics

• Added note 15 in Table 10-16.

• Updated Table 10-18 to include USB 3.1 Gen1(5 GT/s) and USB 3.1 Gen2(10 GT/s) spec.

• Updated signal names in Table 10-22 and Table 10-24.

• Added USB 2.0 undershoot/overshoot spec in Table 10-40.

Chapter 11, Ballout Definition

• Updated information for x4 DMI only support. Removed [7:4] lane and x8 width details.

Chapter 24, Low Pin Count

• Updated the LPC specification link in “References section”

Chapter 26, PCI Express

• Added Precision Time Measurement (PTM) details Chapter 33, Testability

• Added a note in Section 33.3 stating that DCI and kernel level debugger are mutually exclusive

Chapter 38, Direct Media Interface

• Updated information for x4 DMI only support. Removed [7:4] lane and x8 width details.

Chapter 39, Private Configuration Space Target Port ID

• Changed chapter name to “Private Configuration Space Target Port ID”.

• Updated Table 39.1.

August 2018

003 Chapter 2, PCH Controller Device IDs

• Updated Section 2.1.

• Updated Device and Revision ID table.

Chapter 10, Electrical Characteristics

• Updated VOH min Value in Table 10-9.

• Updated I²S timing specification in Table 10-31, Table 10-37 and Table 10-36.

• Updated Figure 10-7, Table 10-24, Table 10-26, Table 10-27, Table 10-28 and Table 10-34.

• Added Table 10-30.

Chapter 22, Low Pin Count

• Updated the LPC specification link in Section 24.2.

• Updated the LPC Interface diagram.

• Updated signal description.

• Updated I/O Signal Planes and States.

Chapter 25, PCH and System Clocks

• Included updated ICC diagrams which show HDA_PLL and XTAL Direct Paths for Display clock generation. Also removed conditional text for CPUNSSC clock descriptions.

• Added missing HM375, QM375, and CM248 details to PCH ICC Clocking. Profile Support table.

Chapter 26, PCI Express* (PCIe*)

Corrected HM370 SKU PCIe* Controller Remapping Details.

August 2018

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004 Chapter 1, Introduction

• Added Z390 details

• Added C242 and C246 SKU details Chapter 2, PCH Controller Device IDs

• Added C242 and C246 SKU details in Table 2-1 Chapter 5, System Management

• Removed “Second hard-coded timer timeout to generate reboot” from Section 5.3, “Features”

• Changed Intel ME to Intel^® CSME

Chapter 10, Electrical and Thermal Characteristics

• Updated Chapter title to “Electrical and Thermal Characteristics”

• Removed PCH Power Supply Range table

• Updated Section 10.2, “Thermal Specification”

• Updated Table 10-1, Table 10-2, Table 10-3, Table 10-4, Table 10-5, Table 10-6, Table 10-9, Table 10-11, Table 10-12, Table 10-14, Table 10-15, Table 10-16

• Updated notes section of Table 10-10

• Updated notes for t108 in Table 10-17

• Updated Figure 10-11

• SPI Clock frequency updated to 50 MHz from 48MHz in Table 10-28

• SPI Touch Timings (17 MHz) table added Table 10-29

• SPI Clock frequency updated to 25 MHz from 20MHz in Table 10-34

• eSPI Timings added (30,48 and 60 MHz) (Table 10-31, Table 10-32, Table 10-33).

Chapter 21, Gigabit Ethernet Controller

• Updated Section 21.2, “References” and Section 21.7,

“Functional Description”

Chapter 24, Low Pin Count (LPC)

• Updated Section 24.2, “References” and Section 24.7.6,

“SYNC Error Indication”

Chapter 25, PCH and System Clocks

• Added C242 and C246 SKU details in Table 25-1

• Added the signal Type for XTAL_Freq_Select in Table 25-1 Chapter 26, PCI Express (PCIe*)

• Added Z390 SKU Figure 26-1

• Removed HM375, QM375, and CM248 SKUs that are no longer supported SKUs

Chapter 28, Real Time Clock (RTC)

• Updated Section 28.5.6 with correct design guide references

• Updated table note in Section 28.4

Chapter 32, Serial Peripheral Interface (SPI)

• Updated Section 32.6.1.3.2, “Flash Descriptor CPU Complex Soft Strap Section”

• Updated Table 32-4

• Updated Section 32.5, “I/O Signal Planes and States”

Chapter 35, Universal Serial Bus (USB)

• Added C242 and C246 SKU details in Figure 35-1 Chapter 40, Secure Digital eXtended Capacity (SDXC)

• Updated Section 40.4, “Signal Description”

• Updated Section 40.5, “I/O Signal Planes and States”

December 2018

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§ §

005 Chapter 10, Electrical and Thermal Characteristics

• Updated Table 10-16 and Table 10-20.

• Added Table 10-21 and Table 10-23.

Chapter 17, Enhanced Serial Peripheral Interface (eSPI)

• Removed information on PECI over eSPI.

Chapter 26, PCI Express (PCIe*)

• Corrected QM370 SKU data table.

Chapter 35, Universal Serial Bus (USB)

• Changed product name on the Supported USB 2.0 Ports table to generic name.

• Changed CNL/CFL to PCH-U/Y.

Chapter 36, Connectivity Integrated (CNVi)

• Updated Section 36.4, “Signal Description” table.

March 2019

006 Chapter 3, Flexible IO

• Corrected USB naming

Chapter 10, Electrical and Thermal Characteristics

• UpdatedT150(min) and T154(min) value in Table 10-24.

Chapter 36, Connectivity Integrated (CNVi)

• Added a Note under signal description table

September 2019

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Introduction

1 Introduction

1.1 About this Manual

This document is intended for Original Equipment Manufacturers (OEMs), Original Design Manufacturers (ODM) and BIOS vendors creating products based on the Intel^® 300 Series and Intel^® C240 Series Chipset Families Platform Controller Hub (PCH).

Throughout this document, the Platform Controller Hub (PCH) is used as a general term and refers to all SKUs, unless specifically noted otherwise.

Throughout this document, PCH refers to desktop, and mobile segment PCH SKUs, unless specifically noted otherwise.

Throughout this document, the terms “Desktop” and “Desktop Only” refers to

information that is applicable only to Desktop PCH, unless specifically noted otherwise.

Throughout this document, the terms “Mobile” and “Mobile Only” refers to information that is applicable only to Mobile PCH, unless specifically noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of

interfaces and architectures such as PCI Express* (PCIe*), Universal Serial Bus (USB), Advance Host Controller Interface (AHCI), eXtensible Host Controller Interface (xHCI), and so on. This manual abbreviates buses as Bn, devices as Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0.

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

• ACPI Power Management Logic Support, Revision 4.0a

• PCI Express* Base Specification Revision 3.0

• Integrated Serial ATA Host Controller 3.2

• xHCI USB 3.1 Controller

• USB Dual Role Capability

• Direct Media Interface (DMI)

• Serial Peripheral Interface (SPI)

• Enhanced Serial Peripheral Interface (eSPI)

• Flexible I/O—Allows some high speed I/O signals to be configured as PCIe*, SATA 6Gb/s or USB 3.1

• General Purpose Input Output (GPIO)

• Low Pin Count (LPC) interface

• Interrupt Controller

• Timer functions

• System Management Bus (SMBus) Specification, Version 2.0

• Integrated Clock Controller (ICC) / Real Time Clock (RTC)

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Introduction

• Intel^® High Definition Audio and Intel^® Smart Sound Technology (Intel^® SST) supporting Intel^® HD Audio, I²S, SoundWire*, and DMIC interfaces

• Intel^® Serial I/O UART Host Controllers

• Intel^® Serial I/O I²C host Controllers

• Integrated 10/100/1000 Gigabit Ethernet MAC

• Integrated Sensor Hub (ISH)

• Supports Intel^® Rapid Storage Technology (Intel^® RST)

• Supports Intel^® Active Management Technology (Intel^® AMT)

• Supports Intel^®Virtualization Technology for Directed I/O (Intel^® VT-d)

• Supports Intel^® Trusted Execution Technology (Intel^® TXT)

• JTAG Boundary Scan support

• Intel^® Trace Hub (Intel^® TH) and Direct Connect Interface (DCI) for debug

• Supports Intel^® Converged Security and Management Engine (Intel^® CSME) with firmware version 12

• Integrated Intel^® Wireless-AC SupportNot all functions and capabilities may be available on all SKUs.

1.3 PCH SKUs

The following table provides an overview of the PCH I/O capabilities.

Table 1-1. Desktop PCH SKUs (Sheet 1 of 2)

Features SKU

Q370 H370 B360 H310 Z390

DMI DMI 3.0 x4 DMI 3.0 x4 DMI 3.0 x4 DMI 2.0 x4 DMI 3.0 x4

SATA 6 Gb/s Ports Up to 6 Up to 6 Up to 6 Up to 4 Up to 6

PCIe Up to 24 Gen 3

lanes

Up to 20 Gen 3 lanes

6 Gen 2 lanes

Up to 24 Gen 3 lanes Total USB Ports

(Maximum USB 3.1 Gen 1)

14 (10) 14 (8) 12 (6) 10 (4) 14 (10)

Maximum USB 3.1 Ports: Gen 2 (10 Gb/s) / Gen 1 (5 Gb/s)

6 / 10 4 / 8 4 /6 0 /4 6 / 10

Total USB 2.0 Ports 14 14 12 10 14

Intel^® Smart Sound

Technology YES YES YES NO YES

Intel^® CSME 12 Corporate Consumer / Consumer /

Consumer Consumer

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Introduction

Intel^® Rapid

Storage Technology YES YES YES YES YES

Intel^® RST for PCIe* Storage Ports¹

3 2 1 0 3

Intel^® RST RAID

Support YES YES NO NO YES

Integrated Intel^® Wireless-AC Support

YES YES YES YES YES

eSPI Chip Select 1 1 1 1 2

Intel^® Trusted Execution Technology

YES NO NO NO NO

Processor PCI Express 3.0 Lanes Configuration Support

1x16 or 2x8 or

1x8+2x4 1x16 1x16 1x16 1x16 or 2x8

or 1x8+2x4

Simultaneous Independent Display Support²

3 3 3 2 3

Notes:

1. Refer to Section 26.4.1 for more information on the Intel^® RST for PCIe* Storage port locations.

2. This is applicable to integrated graphics only.

Table 1-1. Desktop PCH SKUs (Sheet 2 of 2)

Q370 H370 B360 H310 Z390

Table 1-2. Workstation / Server PCH SKUs (Sheet 1 of 2)

Features

SKU

C242 C246

DMI DMI 3.0 x4 DMI 3.0 x4

SATA 6 Gb/s Ports Up to 6 Up to 8

PCIe Up to 10 Gen 3 lanes Up to 24 Gen 3 lanes

Total USB Ports (Maximum USB

3.1 Gen 1) 12 (6) 14 (10)

Maximum USB 3.1 Ports: Gen 2

(10 Gb/s) / Gen 1 (5 Gb/s) 2 / 6 6 / 10

Total USB 2.0 Ports 12 14

Intel^® Smart Sound Technology Yes Yes

Intel^® CSME 12 Firmware Corporate Corporate

Intel^® AMT No Yes

Intel^® Optane™ Memory Support No Yes

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Introduction

Intel^® Rapid Storage Technology

Enterprise Yes Yes

Intel^® RST for PCIe* Storage

Ports¹ 1 3

Integrated Intel^® Wireless-AC

Support Yes Yes

eSPI Chip Select 2 2

Intel^® Trusted Execution

Technology Yes Yes

Simultaneous Independent

Display Support² No Integrated Graphics Support 3

Notes:

Table 1-3. Mobile PCH SKUs (Sheet 1 of 2)

Mobile PCH SKUs SKU

HM370 QM370 CM246

DMI DMI 3.0 x4 DMI 3.0 x4 DMI 3.0 x4

SATA 6 Gb/s Ports 4 4 8

PCIe* Up to 16 Gen 3

lanes

Up to 24 Gen 3 lanes Total USB Ports (Maximum USB 3.1 Gen

1) 14 (8) 14 (10) 14 (10)

Maximum USB 3.1 Ports: Gen 2 (10 Gb/s)

/ Gen 1 (5 Gb/s) 4 / 8 6 / 10 6 / 10

Total USB 2.0 Ports 14 14 14

Intel^® Smart Sound Technology Yes Yes Yes

Intel^® CSME 12 Firmware Consumer Consumer /

Corporate

Consumer / Corporate

Intel^® AMT No Yes Yes

Intel^® Optane™ Memory Support Yes Yes Yes

Intel^® Rapid Storage Technology Yes Yes Yes

Intel^® RST for PCIe Storage Ports¹ 2 2 3

Intel^® RST RAID Support Yes Yes Yes

Table 1-2. Workstation / Server PCH SKUs (Sheet 2 of 2)

C242 C246

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Introduction

Simultaneous Independent Display

Support² 3 3 3

Notes:

Table 1-3. Mobile PCH SKUs (Sheet 2 of 2)

Mobile PCH SKUs SKU

HM370 QM370 CM246

Table 1-4. Desktop PCH HSIO Details (Sheet 1 of 2)

Flex I/O Lane

SKU

Q370 H370 B360 H310 Z390

0 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 USB 3.1 Gen 1 USB 3.1 Gen 1/

Gen 2 1 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 USB 3.1 Gen 1 USB 3.1 Gen 1 / Gen 2 3 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 USB 3.1 Gen 1 USB 3.1 Gen 1 N/A USB 3.1 Gen 1/

Gen 2 6 USB 3.1 Gen 1,

PCIe* USB 3.1 Gen 1 N/A N/A USB 3.1 Gen 1,

PCIe*

7 USB 3.1 Gen 1,

PCIe* USB 3.1 Gen 1 N/A N/A USB 3.1 Gen 1,

PCIe*

8 USB 3.1 Gen 1,

PCIe* PCIe* N/A N/A USB 3.1 Gen 1,

PCIe*

9 USB 3.1 Gen 1,

PCIe* PCIe* N/A N/A USB 3.1 Gen 1,

PCIe*

10 PCIe*, GbE PCIe*, GbE PCIe*, GbE PCIe*, GbE PCIe*, GbE

11 PCIe* PCIe* PCIe* PCIe* PCIe*

14 PCIe*, GbE PCIe*, GbE PCIe*, GbE GbE PCIe*, GbE

15 PCIe* PCIe* PCIe* N/A PCIe*

16 PCIe*, SATA 0A PCIe*, SATA 0A PCIe*, SATA 0A PCIe PCIe*, SATA 0A

17 PCIe*, GbE,

SATA 1A PCIe*, GbE,

SATA 1A PCIe, GbE PCIe*, GbE, SATA 1A

18 PCIe*, GbE,

SATA 0B PCIe*, GbE,

SATA 0B GbE, SATA 0B GbE, SATA 0 PCIe*, GbE, SATA 0B

19 PCIe*, SATA 1B PCIe*, SATA 1B SATA 1B SATA 1 PCIe*, SATA 1B

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Introduction

20 PCIe*, SATA 2 PCIe*, SATA 2 SATA 2 SATA 2 PCIe*, SATA 2

21 PCIe*, SATA 3 PCIe*, SATA 3 SATA 3 SATA 3 PCIe*, SATA 3

22 PCIe*, SATA 4 SATA 4 SATA 4 N/A PCIe*, SATA 4

23 PCIe*, SATA 5 SATA 5 SATA 5 N/A PCIe*, SATA 5

24 PCIe* PCIe* N/A N/A PCIe*

25 PCIe* PCIe* N/A N/A PCIe*

Table 1-5. Workstation / Server PCH HSIO Details (Sheet 1 of 2)

Flex I/O Lane SKU

C242 C246

0 USB 3.1 Gen 1/Gen 2 USB 3.1 Gen 1/Gen 2

1 USB 3.1 Gen 1/Gen 2 USB 3.1 Gen 1/Gen 2

2 USB 3.1 Gen 1 USB 3.1 Gen 1/Gen 2

6 PCIe* USB 3.1 Gen 1,PCIe*

7 PCIe* USB 3.1 Gen 1,PCIe*

8 N/A USB 3.1 Gen 1,PCIe*

9 N/A USB 3.1 Gen 1,PCIe*

10 GbE PCIe*, GbE

11 N/A PCIe*

12 N/A PCIe*

13 N/A PCIe*

14 PCIe*, GbE PCIe*, GbE

15 PCIe PCIe*

16 PCIe*, SATA 0A PCIe*, SATA 0A

17 PCIe*, GbE, SATA 1A PCIe*, GbE, SATA 1A

Table 1-4. Desktop PCH HSIO Details (Sheet 2 of 2)

Q370 H370 B360 H310 Z390

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Introduction

22 SATA 4 PCIe*, SATA 4

23 SATA 5 PCIe*, SATA 5

24 N/A PCIe*, SATA 6

25 N/A PCIe*, SATA 7

26 PCIe* PCIe*

27 PCIe* PCIe*

28 PCIe* PCIe*

29 PCIe* PCIe*

Table 1-6. Mobile PCH HSIO Details (Sheet 1 of 2)

Flex I/O Lane

SKU

HM370 QM370 CM246

0 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 4 USB 3.1 Gen 1 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 5 USB 3.1 Gen 1 USB 3.1 Gen 1/

Gen 2

USB 3.1 Gen 1/

Gen 2 6 USB 3.1 Gen 1 USB 3.1 Gen 1 USB 3.1 Gen 1,

PCIe*

7 USB 3.1 Gen 1 USB 3.1 Gen 1 USB 3.1 Gen 1, PCIe*

8 N/A USB 3.1 Gen 1 USB 3.1 Gen 1,

PCIe*

9 N/A USB 3.1 Gen 1 USB 3.1 Gen 1,

PCIe*

10 GbE PCIe, GbE PCIe*, GbE

11 N/A PCIe* PCIe*

12 N/A PCIe* PCIe*

13 N/A PCIe* PCIe*

14 PCIe*, GbE PCIe*, GbE PCIe*, GbE

15 PCIe* PCIe* PCIe*

16 PCIe*, SATA 0A PCIe*, SATA 0A PCIe*, SATA 0A

Table 1-5. Workstation / Server PCH HSIO Details (Sheet 2 of 2)

C242 C246

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Introduction

§ §

17 PCIe*, GbE, SATA 1A

PCIe*, GbE, SATA 1A

PCIe*, GbE, SATA 1A 18 PCIe*, GbE,

SATA 0B

PCIe*, GbE, SATA 0B

PCIe*, GbE, SATA 0B 19 PCIe*, SATA 1B PCIe*, SATA 1B PCIe*, SATA 1B

20 PCIe* PCIe* PCIe*, SATA 2

22 PCIe*, SATA 4 PCIe*, SATA 4 PCIe*, SATA 4 23 PCIe*, SATA 5 PCIe*, SATA 5 PCIe*, SATA 5

Table 1-6. Mobile PCH HSIO Details (Sheet 2 of 2)

Flex I/O Lane

SKU

HM370 QM370 CM246

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PCH Controller Device IDs

2 PCH Controller Device IDs

2.1 Device and Revision ID Table

The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI header of every PCIe* function.

Table 2-1. PCH Device and Revision ID Table (Sheet 1 of 2)

Dev ID Device Function - Device Description B0 SRID Notes

A300 - A31F D31:F0 - LPC Controller (eSPI Enable Strap = 0)/

eSPI Controller (eSPI Enable Strap = 1) 10

PCH Device IDs:

Q370: A306 H370: A304 Z390: A305 B360: A308 H310: A303 C242: A30A C246: A309 HM370: A30D QM370: A30C CM246: A30E

A320 D31:F1 - P2SB 10

A321 D31:F2 - PMC 10

A323 D31:F4 - SMBus 10

A324 D31:F5 - SPI (Flash) Controller 10

15BB D31:F6 - GbE Controller 10

15BC D31:F6 - GbE Controller: Consumer 10

A326 D31:F7 - Intel^® Trace Hub 10

A328 D30:F0 - UART #0 10

A329 D30:F1 - UART #1 10

A32A D30:F2 - GSPI #0 10

A32B D30:F3 - GSPI #1 10

A32C D27:F4 - PCI Express* Root Port #21 F0

A32D D27:F5 - PCI Express* Root Port #22 F0

A32E D27:F6 - PCI Express* Root Port #23 F0

A32F D27:F7 - PCI Express* Root Port #24 F0

A330 D29:F0 - PCI Express* Root Port #9 F0

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PCH Controller Device IDs

A33A D28:F2 - PCI Express* Root Port #3 F0

A33B D28:F3 - PCI Express* Root Port #4 F0

A33C D28:F4 - PCI Express* Root Port #5 F0

A33D D28:F5 - PCI Express* Root Port #6 F0

A33E D28:F6 - PCI Express* Root Port #7 F0

A33F D28:F7 - PCI Express* Root Port #8 F0

A347 D25:F2 - UART #2 10

A348 D31:F3 - cAVS 10

A352 D23:F0 - SATA Controller (AHCI) 10 Desktop SKUs: Q370, H370, B360, H310, Z390, C242, C246.

A353 D23:F0 - SATA Controller (AHCI) 10 Mobile H SKUs: HM370, QM370, CM246.

A355 D23:F0 - SATA Controller (RAID 0/1/5/10) 10 Mobile H SKUs: HM370, QM370, CM246.

A356 D23:F0 - SATA Controller (RAID 0/1/5/10) 10 Desktop SKUs: Q370, H370, B360, H310, Z390, C242, C246.

A357 D23:F0 - SATA Controller (RAID 0/1/5/10) 10 Mobile H SKUs: HM370, QM370, CM246.

2822 D23:F0 - SATA Controller (RAID 0/1/5/10) -

Intel ® 300 Series and Intel ® C240 Series Chipset Family Platform