21 Gigabit Ethernet Controller
21.7 Functional Description
The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel® Ethernet Connection I219. The integrated GbE controller provides two interfaces for 10/100/1000 Mbps and manageability operation:
• Data link based on PCIe* – A high-speed interface that uses PCIe* electrical signaling at half speed and custom logical protocol for active state operation mode.
• System Management Link (SMLink0)—A low speed connection for low power state mode for manageability communication only. The frequency of this connection can be configured to one of three different speeds (100 kHz, 400 kHz or 1 MHz).
The Intel® Ethernet Connection I219 only runs at a speed of 1250 Mbps, which is 1/2 of the 2.5 Gb/s PCI Express frequency. Each of the PCIe* root ports in the PCH have the ability to run at the 1250-Mbps rate. There is no need to implement a mechanism to detect that the Platform LAN Device is connected. The port configuration (if any), attached to the Platform LAN Device, is pre-loaded from the NVM. The selected port adjusts the transmitter to run at the 1250 Mbps rate and does not need to be PCIe*
compliant.
Note: PCIe* validation tools cannot be used for electrical validation of this interface—
however, PCIe* layout rules apply for on-board routing.
The integrated GbE controller operates at full-duplex at all supported speeds or half-duplex at 10/100 Mbps. It also adheres to the IEEE 802.3x Flow Control Specification.
Note: GbE operation (1000 Mbps) is only supported in S0 mode. In Sx modes, the platform LAN Device may maintain 10/100 Mbps connectivity and use the SMLink interface to communicate with the PCH.
The integrated GbE controller provides a system interface using a PCIe* function. A full memory-mapped or I/O-mapped interface is provided to the software, along with DMA mechanisms for high performance data transfer.
The integrated GbE controller features are:
• Network Features
— Compliant with the 1 Gb/s Ethernet IEEE 802.3, IEEE 802.3u, IEEE 802.3ab specifications
— Multi-speed operation: 10/100/1000 Mbps
— Full-duplex operation at 10/100/1000 Mbps: Half-duplex at 10/100 Mbps
— Flow control support compliant with the 802.3X specification
— VLAN support compliant with the 802.3q specification
— MAC address filters: perfect match unicast filters; multicast hash filtering, broadcast filter and promiscuous mode
— PCIe*/SMLink interface to GbE PHYs
• Host Interface Features
— 64 bit address master support for systems using more than 4 GB of physical memory
— Programmable host memory receive buffers (256 bytes to 16 KB)
— Intelligent interrupt generation features to enhance driver performance
— Descriptor ring management hardware for transmit and receive
— Software controlled reset (resets everything except the configuration space)
— Message Signaled Interrupts
Gigabit Ethernet Controller
• Performance Features
— Configurable receive and transmit data FIFO, programmable in 1 KB increments
— TCP segmentation off loading features
— Fragmented UDP checksum off load for packet reassembly
— IPv4 and IPv6 checksum off load support (receive, transmit, and large send)
— Split header support to eliminate payload copy from user space to host space
— Receive Side Scaling (RSS) with two hardware receive queues
— Supports 9018 bytes of jumbo packets
— Packet buffer size 32 KB
— TimeSync off load compliant with IEEE 802.1as specification
— Platform time synchronization
• Power Management Features
— Magic Packet* wake-up enable with unique MAC address
— ACPI register set and power down functionality supporting D0 and D3 states
— Full wake up support (APM, ACPI)
— MAC power down at Sx, DM-Off with and without WoL
— Auto connect battery saver at S0 no link and Sx no link
— Energy Efficient Ethernet (EEE) support
— Latency Tolerance Reporting (LTR)
— ARP and ND proxy support through LAN Connected Device proxy
— Wake on LAN (WoL) from Deep Sx
— Windows* InstantGo* Support
21.7.1 GbE PCI Express* Bus Interface
The GbE controller has a PCIe* interface to the host processor and host memory. The following sections detail the bus transactions.
21.7.1.1 Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device GbE controller using an implementation specific protocol.
Through this GbE controller-to-transaction-layer protocol, the application-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively.
21.7.1.2 Data Alignment 21.7.1.2.1 4 KB Boundary
PCI requests must never specify an address/length combination that causes a memory space access to cross a 4-KB boundary. It is hardware’s responsibility to break requests into 4 KB aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4 KB boundary, hardware issues multiple requests for the buffer. Software should consider aligning buffers to a 4 KB boundary in cases where it improves performance. The alignment to the 4 KB boundaries is done by the GbE controller. The transaction layer does not do any alignment according to these boundaries.
Gigabit Ethernet Controller
21.7.1.2.2 PCI Request Size
PCI requests are 128 bytes or less and are aligned to make better use of memory controller resources. Writes, however, can be on any boundary and can cross a 64-byte alignment boundary.
21.7.1.3 Configuration Request Retry Status
The integrated GbE controller might have a delay in initialization due to an NVM read. If the NVM configuration read operation is not completed and the device receives a configuration request, the device responds with a configuration request retry
completion status to terminate the request, and thus effectively stalls the configuration request until such time that the sub-system has completed local initialization and is ready to communicate with the host.
21.7.2 Error Events and Error Reporting
21.7.2.1 Completer Abort Error Handling
A received request that violates the LAN Controller programing model will be discarded, for non posted transactions an unsuccessful completion with CA completion status will be returned. For posted transactions if both SERR# enable and URRE# enable are enabled, the LAN Controller will assert SERR#.
21.7.2.2 Unsupported Request Error Handling
A received unsupported request to the LAN Controller will be discarded, for non posted transactions an unsuccessful completion with UR completion status will be returned.
The URD bit will be set in ECTL register, If both SERR# enable and URRE# enable are enabled, the LAN Controller will assert SERR#. For posted transactions, if both SERR#
enable and URRE# enable are enabled, the LAN Controller will assert SERR#.
21.7.3 Ethernet Interface
The integrated GbE controller provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mbps), IEEE 802.3u (100 Mbps) implementations. It also supports the IEEE 802.3z and IEEE 802.3ab (1000 Mbps) implementations. The device performs all of the functions required for transmission, reception, and collision handling called out in the standards.
The mode used to communicate between the PCH and the Intel® Ethernet Connection I219 supports 10/100/1000 Mbps operation, with both half- and full-duplex operation at 10/100 Mbps, and full-duplex operation at 1000 Mbps.
21.7.3.1 Intel® Ethernet Connection I219
The integrated GbE controller and the Intel® Ethernet Connection I219 communicate through the PCIe* and SMLink0 interfaces. All integrated GbE controller configuration is performed using device control registers mapped into system memory or I/O space.
The Platform LAN Phy is configured using the PCI Express or SMLink0 interface.
The integrated GbE controller supports various modes as listed in Table 21-5.
Gigabit Ethernet Controller
21.7.4 PCI Power Management
The integrated GbE controller supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This enables the network-related activity (using an internal host wake signal) to wake up the host. For example, from Sx (S3–S5) and Deep Sx to S0.
Note: The Intel® Ethernet Connection I219 must be powered during the Deep Sx state in order to support host wake up from Deep Sx. GPD_2_LAN_WAKE# on the PCH must be configured to support wake from Deep Sx and must be connected to LANWAKE_N on the Platform LAN Connect Device. The SLP_LAN# signal must be driven high (de-asserted) in the Deep Sx state to maintain power to the Platform LAN Connect Device.
The integrated GbE controller contains power management registers for PCI and supports D0 and D3 states. PCIe* transactions are only allowed in the D0 state, except for host accesses to the integrated GbE controller’s PCI configuration registers.
Note: SLP_LAN# pin behavior are detailed in Section 27.7.10.5, “SLP_LAN# Pin Behavior”.
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Table 21-5. LAN Mode Support
Mode System State Interface Active Connections
Normal 10/100/1000 Mbps S0 PCIe* Intel® Ethernet
Connection I219
Manageability and Wake-on-LAN Sx SMLink0 Intel® Ethernet
Connection I219
Wake-on-LAN Deep Sx LAN_WAKE# Intel® Ethernet
Connection I219
Interrupt Interface