Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH)
23.4 Signal Description
23.5 Integrated Pull-Ups and Pull-Downs
Name Type Description
ISH_I2C0_SDA/GPP_H19 I/OD ISH I2C 0 Data
ISH_I2C0_SCL/GPP_H20 I/OD ISH I2C 0 Clk
ISH_I2C1_SDA/GPP_H21 I/OD ISH I2C 1 Data
ISH_I2C1_SCL/GPP_H22 I/OD ISH I2C 1 Clk
ISH_I2C2_SDA / GPP_D4 / I2C3_SDA / SBK4 / BK4 I/OD ISH I2C 2 Data ISH_I2C2_SCL / GPP_D23 / I2C3_SCL I/OD ISH I2C 2 Clk
ISH_GP0/GPP_A18 I/O ISH GPIO 0
ISH_GP1/GPP_A19 I/O ISH GPIO 1
ISH_GP2/GPP_A20 I/O ISH GPIO 2
ISH_GP3/GPP_A21 I/O ISH GPIO 3
ISH_GP4/GPP_A22 I/O ISH GPIO 4
ISH_GP5/GPP_A23 I/O ISH GPIO 5
ISH_GP6 / GPP_A12 / BM_BUSY# / SX_EXIT_HOLDOFF# I/O ISH GPIO 6 ISH_GP7/ GPP_A17 / SD_VDD1_PWR_EN# I/O ISH GPIO 7
ISH_UART0_TXD / GPP_D14 / I2C2_SCL O ISH UART 0 Transmit Data ISH_UART0_RXD /GPP_D13 / I2C2_SDA I ISH UART 0 Receive Data ISH_UART0_RTS# /GPP_D15 / GSPI2_CS1# /
CNV_WFEN O ISH UART 0 Request To Send
ISH_UART0_CTS# /GPP_D16 / CNV_WCEN I ISH UART 0 Clear to Send ISH_UART1_TXD /GPP_C13 / UART1_TXD O ISH UART 1 Transmit Data ISH_UART1_RXD /GPP_C12 / UART1_RXD I ISH UART 1 Receive Data ISH_UART1_RTS# /GPP_C14 / UART1_RTS# O ISH UART 1 Request To Send ISH_UART1_CTS# / GPP_C15 / UART1_CTS# I ISH UART 1 Clear to Send ISH_SPI_CS# / GPP_D9 / GSPI2_CS0# O ISH SPI 2 Chip Select ISH_SPI_CLK / GPP_D10 / GSPI2_CLK O ISH SPI 2 Clock ISH_SPI_MISO / GPP_D11 / GSPI2_MISO /
GP_BSSB_CLK I ISH SPI 2 MISO
ISH_SPI_MOSI / GPP_D12 / GSPI2_MOSI / GP_BSSB_DI
O ISH SPI 2 MOSI Note: This signal is also
utilized as a strap. Refer the pin strap chapter for more info.
Integrated Sensor Hub (ISH)
23.6 I/O Signal Planes and States
23.7 Functional Description
23.7.1 ISH Micro-Controller
The ISH is operated by a micro-controller. This core provides localized sensor
aggregation and data processing, thus off loading the processor and lowering overall platform average power. The core supports an in-built local APIC that receives messages from the IOAPIC. A local boot ROM with FW for initialization is also part of the core.
23.7.2 SRAM
The local SRAM is used for ISH FW code storage and to read/write operational data.
The local SRAM block includes both the physical SRAM as well as the controller logic.
The SRAM is a total of 640 kbytes organized into banks of 32 kB each and is 32-bit wide. The SRAM is shared with Intel® CSME as shareable memory. To protect against memory errors, the SRAM includes ECC support. The ECC mechanism is able to detect multi-bit errors and correct for single bit errors. The ISH firmware has the ability to put unused SRAM banks into lower power states to reduce power consumption.
Table 23-1. I/O Signal Planes and States
Signal Name Power Plane During Reset* Immediately
after Reset* S3/S4/S5 Deep Sx
ISH_I2C0_SDA Primary Undriven Undriven Undriven OFF
ISH_I2C0_SCL Primary Undriven Undriven Undriven OFF
ISH_I2C1_SDA Primary Undriven Undriven Undriven OFF
ISH_I2C1_SCL Primary Undriven Undriven Undriven OFF
ISH_I2C2_SDA Primary Undriven Undriven Undriven OFF
ISH_I2C2_SCL Primary Undriven Undriven Undriven OFF
ISH_GP[7:0] Primary Undriven Undriven Undriven OFF
ISH_UART0_TXD Primary Undriven Undriven Undriven OFF
ISH_UART0_RXD Primary Undriven Undriven Undriven OFF
ISH_UART0_RTS# Primary Undriven Undriven Undriven OFF
ISH_UART0_CTS# Primary Undriven Undriven Undriven OFF
ISH_UART1_TXD Primary Undriven Undriven Undriven OFF
ISH_UART1_RXD Primary Undriven Undriven Undriven OFF
ISH_UART1_RTS# Primary Undriven Undriven Undriven OFF
ISH_UART1_CTS# Primary Undriven Undriven Undriven OFF
ISH_SPI_CS# Primary Undriven Undriven Undriven OFF
ISH_SPI_CLK Primary Undriven Undriven Undriven OFF
ISH_SPI_MISO Primary Undriven Undriven Undriven OFF
ISH_SPI_MOSI Primary Undriven Undriven Undriven OFF
Note: *Reset reference for primary well pins is RSMRST#, DSW well pins is DSW_PWROK, and RTC well pins is RTCRST#.
Integrated Sensor Hub (ISH)
23.7.3 PCI Host Interface
The ISH provides access to PCI configuration space via a PCI Bridge. Type 0 Configuration Cycles from the host are directed to the PCI configuration space.
23.7.3.1 MMIO Space
A mapped Base Address Register (BAR0) with a set of functional memory-mapped registers is accessible to the host via the Bridge. These registers are owned by the driver running on the Host OS.
The bridge also supports a second BAR (BAR1) that is an alias of the PCI Con figuration space. It is used only in ACPI mode (that is, when the PCI con figuration space is hidden).
23.7.3.2 DMA Controller
The DMA controller supports up to 64-bit addressing.
23.7.3.3 PCI Interrupts
The PCI bridge supports standard PCI interrupts, delivered using IRQx to the system IOAPIC and not using an MSI to the host CPU.
23.7.3.4 PCI Power Management PME is not supported in ISH.
23.7.4 Power Domains and Management
23.7.4.1 ISH Power Management
The various functional blocks within the ISH are all on the primary power plane within the PCH. The ISH is only intended for use during S0 and S0ix states. There is no support for operation in S3, S4, or S5 states. Thus, the system designer must ensure that the inputs to the ISH signals are not driven high while the PCH is in S3–S5 state.
The unused banks of the ISH SRAM can be power-gated by the ISH Firmware.
23.7.4.2 External Sensor Power Management
External sensors can generally be put into a low power state through commands issued over the I/O interface (I2C). Refer to the datasheets of the individual sensors to obtain the commands to be sent to the peripheral.
23.7.5 ISH IPC
The ISH has IPC channels for communication with the Host Processor and Intel® CSME.
The functions supported by the ISH IPC block are listed below.
Function 1: Allows for messages and interrupts to be sent from an initiator (such as
Integrated Sensor Hub (ISH)
Table 23-2. IPC Initiator -> Target flows
Function 2: Provides status registers and remap registers that assist in the boot flow and debug. These are simple registers with dual access read/write support and cause no interrupts.
23.7.6 ISH Interrupt Handling via IOAPIC (Interrupt Controller)
The PCH legacy IOAPIC is the interrupt controller for the ISH. It collects inputs from various internal blocks and sends interrupt messages to the ISH controller. When there is a change on one of its inputs, the IOAPIC sends an interrupt message to the ISH controller.
The PCH IOAPIC allows each interrupt input to be active high or active low and edge or level triggered.
23.7.7 ISH I
2C Controllers
The ISH supports three I2C controllers capable of operating at speeds up to 2.4 Mbps each. The I2C controllers are completely independent of each other: they do not share any pins, memory spaces, or interrupts.
The ISH’s I2C host controllers share the same general specifications:
• Master Mode Only (all peripherals must be slave devices)
• Support for the following operating speeds:
— Standard mode: 100 kbps
— Fast Mode: 400 kbps
— Fast Mode Plus: 1 000 kbps
— High Speed Mode: 2400 kbps
• Support for both 7-bit and 10-bit addressing formats on the I2C bus
• FIFO of 64 bytes with programmable watermarks/thresholds
23.7.8 ISH UART Controller
The ISH has two UART ports, each comprised of a four-wire, bi-directional point-to-point connection between the ISH and a peripheral.
The UART has the following Capabilities:
• Support for operating speeds up to 4 Mbps
• Support for auto flow control using the RTS#/CTS# signals
• 64-byte FIFO
Initiator Target
ISH Host processor
Host processor ISH
ISH Intel® CSME
Intel® CSME ISH
Integrated Sensor Hub (ISH)
• DMA support to allow direct transfer to the ISH local SRAM without intervention by the controller. This saves interrupts on packets that are longer than the FIFO or when there are back-to-back packets to send or receive.
23.7.9 ISH GSPI Controller
The ISH supports one SPI controller comprises of four-wired interface connecting the ISH to external sensor devices.
The SPI controller includes:
• Master Mode Only
• Single Chip Select
• Half Duplex operation only
• Programmable SPI clock frequency range with maximum rate of 24 Mbits/sec
• FIFO of 64 bytes with programmable thresholds
• Support Programmable character length (2 to 16 bits)
23.7.10 ISH GPIOs
The ISH supports eight dedicated GPIOs.
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Low Pin Count (LPC)